Frequency driven layout system and method for field programmable

Details Frequency driven layout system and method for field programmable Frequency driven layout system and method for field programmable

1995-02-06

1997-07-15

Teska, Kevin J.

Boots, shoes, and leggings

364488, G06F 1750

Patent

active

056489137

ABSTRACT:
A device independent, frequency driven layout system and method for field programmable gate arrays ("FPGA") which allow for a circuit designer to specify the desired operating frequencies of clock signals in a given design to the automatic layout system to generate, if possible, a physical FPGA layout which will allow the targeted FPGA device to operate at the specified frequencies. Actual net, path and skew requirements are automatically generated and fed to the place and route tools. The system and method of the present invention evaluates the frequency constraints, determines what delay ranges are acceptable for each electrical connection and targets those ranges throughout the layout.

REFERENCES:
patent: 5003487 (1991-03-01), Drumm et al.
patent: 5095454 (1992-03-01), Huang
patent: 5210700 (1993-05-01), Tom
patent: 5218551 (1993-06-01), Agrawal et al.
patent: 5521837 (1996-05-01), Frankle et al.
Agrawal., "Synchronous Path Analysis in MOS Circuit Simulator," 1982 19th Design Automation Conference, Paper 35.4, pp. 629-635.
Brown et al., "A Stochastic Model to Predict the Routability of FPGAs," IEEE Trans. on CAD of Ics and Systems, vol. 12, No. 12, Dec. 1993, (Jan. 1993), pp. 1827-1838.
Brown et al., "A Detailed Router for FPGAs," IEEE Trans. on CAD, vol. 11, No. 5, May 1992, pp. 620-628.
Donath et al., "Timing Driven Placement Using Complete Path Delays," 1990 27th ACM/IEEE Design Automation Conference, Paper 6.1, pp. 84-89.
Frankle, "Iterative and Adaptive Slack Allocation for Performance-Driven Layout and FPGA Routing," 1992 29th ACM/IEEE Design Automation Conference, Paper 34.1, pp. 536-542.
Jackson et al., "Performance-Driven Placement of Cell Based IC's," 1989 26th ACM/IEEE Design Automation Conference, Paper 24.2, pp. 370-375.
Jouppi, "Timing Analysis for nMOS VLSI," 1983 20th Design Automation Conference, Paper 27.3, pp. 411-418.
Rubinstein et al., "Signal Delay in RC Tree Networks," IEEE Trans. on CAD, vol. CAD-2, No. 3, Jul. 1983, pp. 202-211.
Schlag et al., "Empirical Evaluation of Multilevel Logic Minimization Tools for a Lookup-Table-Based FPGA Technology," IEEE Trans. on CAD of ICs and Systems, vol. 12, No. 5, (Jun. 1991), pp. 713-722, May 1993.
Singh et al., "Optimization of FPGA Logic Block Architecture for Speed," IEEE 1991 Custom Ics Conference, pp. 6.1.1-6.1.6.
Teig et al., "Timing-Driven Layout of Cell-Based Ics," VLSI Systems Design, May 1986, pp. 63-73.
Youssef et al., "Timing Constraints for Correct Performance," 1990 IEEE, pp. 24-27.

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