Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2006-11-07
2006-11-07
Iqbal, Nadeem (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C327S047000
Reexamination Certificate
active
07134042
ABSTRACT:
A frequency detection circuit according to the present invention has a status holding register for storing rise information and fall information about a check target clock and outputting an error detection signal showing frequency abnormality when information showing the next edge (a fall or a rise) from a rise or a fall of the check target clock is not stored, a rise/fall detection circuit for respectively detecting a rise and a fall of the check target clock and outputting a rise detection signal in response to the rise and a fall detection signal in response to the fall, a sampling clock generation circuit for generating sampling clock for storing the information about the check target clock, and an edge detection signal generation circuit for outputting an edge detection signal which is an edge detection result of the check target clock based on the rise detection signal and the fall detection signal.
REFERENCES:
patent: 5381416 (1995-01-01), Vartti et al.
patent: 5657361 (1997-08-01), Inagaki et al.
patent: 6333646 (2001-12-01), Tsuzuki
English translation of relevant portions of Examiner's comments in Japanese Office Action issued Apr. 6, 2005 submitted in lieu of statement of relevancy of prior art to present invention.
English translation of relevant portions of Examiner's comments in Japanese Office Action issued Apr. 5, 2006 submitted in lieu of statement of relevancy of prior art to present invention.
Iqbal Nadeem
NEC Electronics Corporation
Ostrolenk Faber Gerb & Soffen, LLP
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