Frequency decoder databank for phase-locked loop

Details Frequency decoder databank for phase-locked loop Frequency decoder databank for phase-locked loop

1997-11-13

2001-09-18

Pham, Chi (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S226000

Reexamination Certificate

active

06292522

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to phase-locked loop testing. In particular, the present invention relates to testing the voltage-controlled oscillator of a phase-locked loop cell.
Phase-locked loop (PLL) cells are commonly used in data receivers to generate square-wave clock signals that have frequencies equal to the frequency of the incoming data. To accommodate variations in the frequency of the transmitted data, a phase detector in the PLL cell continuously monitor the data and the clock signal. The phase detector creates a voltage based on the phase difference between the two signals and this voltage is used to drive a voltage-controlled oscillator, which produces the square-wave clock signal in response to the voltage.
Before shipping a PLL cell, the voltage-controlled oscillator is tested to ensure that it is operating properly. To accomplish this frequency testing, the art attaches a counter to the output of the voltage-controlled oscillator and stimulates the oscillator so that it produces an oscillating signal. Each positive-going transition in the oscillating signal causes the counter to increment by one. When the counter reaches a specific count, its output transitions from LOW to HIGH. The amount of time that passed between when the voltage-controlled oscillator was first activated and when the counter output became HIGH is indicative of the frequency of the clock signal.
In the art, such counters are used because they allow frequency testing to be accomplished using a series of test vectors. Each test vector occurs at a specific time during testing and includes the input values provided to the PLL cell and the binary output values expected to be produced by the cell at that particular instant in testing.
Although test vectors provide an automated means for testing the frequency of the voltage-controlled oscillator, they typically only provide “GO”, “NO-GO” testing where the PLL cell either passes or fails the test. The test vectors do not convey the actual frequency of the voltage-controlled oscillator's signal. They only state that the frequency is too high, too low, or within an accepted range of frequencies.
The initial acceptable range of frequencies is taken from the data books for the PLL cell. However, these initial ranges often do not fully account for process and temperature variations. To accommodate these variations, the art measures the number of cells that fail the frequency test, and if the number is too high, adjusts the acceptable range of frequencies for the voltage-controlled oscillator. However, because test vectors do not provide information about the actual frequencies of the oscillators, it is impossible to determine a distribution of actual frequencies. As such, a change made to the acceptable frequency range is often nothing more than a guess and several iterations are needed before the proper range is achieved.
This is extremely time consuming and costly because each change in the frequency range requires changes to the test vectors and these test vector changes typically must be made by a design engineer who is located away from the test floor.
SUMMARY OF THE INVENTION
A phase-locked loop cell includes a voltage-controlled oscillator adapted to produce an oscillating signal. A test input to the phase-locked loop is adapted to cause the voltage-controlled oscillator to generate a test oscillating signal. A frequency decoder is coupled to the output of the voltage controlled oscillator and is adapted to provide a voltage related to the frequency of the test oscillating signal.


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