Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2000-09-22
2004-09-14
Chin, Stephen (Department: 2634)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S376000, C370S516000, C327S159000, C327S160000
Reexamination Certificate
active
06792063
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a frequency control and phase lock circuit. More particularly, it relates to a frequency control and phase lock circuit which is capable of high-speed and stable phase synchronization pull-in reproduction of a clock for reproducing a digital signal which is recorded on an optical disk medium, utilizing a linear velocity cycle detected from a reproduced signal, also in a situation where the linear velocity cycle of the reproduced signal varies.
BACKGROUND ART
As a method of recording digital data on an optical disk medium, a method in which the recording is performed at a constant linear velocity to equalize the recording density on the recording medium is used in many cases as can be seen in the case of CDs (Compact Disks) or DVDs. In a case where the phase synchronization pull-in is performed for an optical disk reproduced signal which was subjected to the mark-length modulation and digital modulation to obtain a constant linear recording density, when the difference between the frequency of the clock component of the reproduced signal and the frequency of the clock generated by a phase-locked loop circuit is large, there is a great risk of uncompleted phase synchronization pull-in or pseudo pull-in to a frequency which is different from that of the clock component of the reproduced signal. In order to avoid these situations, the reproduction linear velocity cycle is detected on the basis of the pulse length or pulse interval of a specific pulse included in the reproduced signal, and control of the rotational speed of the disc or control of the free-running frequency of the phase-locked loop is performed, whereby the normal phase synchronization pull-in can be realized.
For example, there is a disc reproduction system as shown in FIG.
12
. Data as shown in FIG.
14
(
a
) are recorded on an optical disk
47
so as to have a constant linear recording density. Assume that the recorded data are controlled to have 3 or more and 14 or less consecutive “0”s or “1”s, as in the 8-16 modulation system. The amplitude of a signal which is reproduced by a reproduction means
48
is attenuates in higher-band frequency components due to the interference, as the linear recording density of the recorded data increases. Thus, this signal is subjected to the compensation by a waveform equalization means
1
to emphasize the higher-band frequency components. The emphasized reproduced signal (FIG.
14
(
b
)) is binarized at a predetermined slice level by a binarization means
49
, to be converted into a binarized digital signal (FIG.
14
(
c
)).
Then, a cycle detection means
50
counts the cycle of a specific pattern of the digital signal which was binarized by the binarization means
49
, using a high-frequency clock. The high frequency clock which is used here is generated by an oscillator
51
. In this case, the oscillator
51
is a crystal oscillator which stably oscillates at a fixed frequency, or the like. As shown in
FIG. 13
, the cycle detection means
50
consists of a counter means
52
continuously counting a pulse width or pulse interval of a specific pulse which is counted using the high-frequency clock, a holding means
53
holding a count result which is just previously obtained by the counter means
52
, an addition means
54
receiving a result which is output by the counter means
52
and the data which are held and output by the holding means
53
, and adding the two consecutive counted pulse width or pulse interval results, and a judgement means
55
obtaining the maximum value or minimum value of the outputs of the addition means
54
at every predetermined period. The cycle detection means
50
obtains the maximum value or minimum value of the sum of the two consecutive pulse widths (or pulse intervals). The information obtained by the cycle detection means
50
is inversely proportional to the linear velocity and includes cycle information of the clock of the reproduced signal. Therefore, the control is performed on the basis of this information so that the free-running frequency of the phase-locked loop circuit
56
nearly matches the frequency of the clock component of the reproduced signal. In this case, a phase-locked loop circuit
56
consists of a phase comparator
57
, a charge pump
58
, a loop filter
59
and a VCO.
60
. This VCO
60
adaptively operates the center frequency on the basis of the frequency information obtained by the cycle detection means
50
, and performs the control so that the oscillated frequency almost matches the frequency of the clock component of the digital signal which is obtained by the binarization means
49
. Thereby, the phase synchronization pull-in can be completed without waiting until the rotation of a motor is settled near the stationary rotation at a timing of starting the reproduction of the disc or immediately after the seek at the CLV reproduction time when the reproduction is performed at a constant linear velocity.
For example in the CAV reproduction in which data are reproduced with fixing the rotation speed of the motor for rotating the recording medium, the linear velocity of the reproduced data varies according to whether an accessed area is on an inner track or outer track of the disc. Assume that the frequency which is synchronized with that of the reproduced data is 20 MHz at an inner track position A and 40 MHz at an outer track position B as shown in
FIG. 15
, and the high-frequency clock which is output by the oscillator
51
is at 100 MHz. In this case, when a DVD is reproduced, the reproduced signal has a synchronization pattern consisting of contiguous 14T and 4T as shown in FIG.
16
(
a
) at regular periods. Here, T is a period corresponding to 1 bit of a recording code included in the reproduced signal. When the pattern length of this synchronization pattern is counted using a 100-MHz high frequency clock, a detected count value is (14+4)×100/20=90 at the inner track position A as shown in FIG.
16
(
b
) and (14+4) ×100/40=45 at the outer track position B as shown in FIG.
16
(
c
). Therefore, it is understood that the count value obtained using the high-frequency clock is information which is inversely proportional to the linear velocity at the reproduction position. Utilizing this principle, assuming that the data at the outer track position B are sought in a state where the data at the inner track position A are being reproduced, the reproduction clock which is output by the VCO
60
is at 20 MHz just after the seeking, which is the phase-locked frequency at the inner track position A, as shown in FIG.
17
. However, when the synchronization pattern is counted using the 100-MHz high-frequency clock and the obtained count number is 45, the feedback is performed so that the reproduction clock output by the VCO
60
approaches 40 MHz according to estimates from the cycle information. The processing is performed up to the area where the phase synchronization pull-in can be performed. Then, the phases of the reproduced data and reproduction clock can be synchronized by the phase-locked loop circuit
56
.
However, when the high-frequency clock is used in the above-described means for detecting the cycle from the reproduced signal, the oscillator for generating the high-frequency clock is required. In addition, when the reproduction is to be performed at higher speed with an increased rotation of the motor, it is required to calculate the cycle according to the reproduction speed. On the other hand, in order to simplify the cycle calculation, it is required to change the oscillated frequency of the high-frequency clock in proportion to the rotational speed of the motor. Further, in order to improve the precision of the cycle detection means, it is desirable to utilize the pattern length and pattern interval of synchronization patterns which are included in the recorded data at regular intervals. However, in the case where the detection of the pattern length and pattern interval of the synchronization patterns is used for det
Chin Stephen
Ha Dac V.
Wenderoth , Lind & Ponack, L.L.P.
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