Frequency and voltage scaling architecture

Details Frequency and voltage scaling architecture Frequency and voltage scaling architecture

2004-11-29

2008-10-07

Connolly, Mark (Department: 2115)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S300000, C713S322000, C713S323000, C713S500000

Reexamination Certificate

active

07434073

ABSTRACT:
A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain independently of the others.

REFERENCES:
patent: 7194643 (2007-03-01), Gonzalez et al.
patent: 2006/0117202 (2006-06-01), Magklis et al.
patent: 2007/0016817 (2007-01-01), Albonesi et al.
patent: PCT/US2005/041392 (2006-09-01), None
Anoop Iyer and Diana Marculescu; “Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors”; 2002.
Greg Semeraro, Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling, Proceedings Eighth International Symposium on High Performance Computer Architecture, 2002, 29-40, XP002399255, IEEE Computer, Los Alamitos, CA.
Diana Marculescu, Application Adaptive Energy Efficient Clustered Architectures, Proceedings of the 2004 International Symposium on Low Power Electronics and Design, Aug. 9, 2004, 344-349, XP010764380, International Symposium on Low Power Electronics and Design, New York, New York.
Examination Report under Section 18(3) dated Nov. 6, 2007 from the UK Intellectual Property Office, pp. 1-4.
Anoop Iyer, et al., “Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors,” 2002 , pp. 1-11.
Greg Semeraro, et al., “Hiding Synchronization Delays In A GALS Processor Microarchitecture,” 2004, pp. 1-13.
Joan-Manuel Parcerisa, et al., “Efficient Interconnects For Clustered Microarchitectures,” 2002, pp. 1-10.
Grigorios Magklis, et al., “Profile-Based Dynamic Voltage And Frequency Scaling For A Multiple Clock Domain Microprocessor,” 2003, pp. 1-12.
Greg Semeraro, et al., “Dynamic Frequency And Voltage Control For A Multiple Clock Domain Microarchitecture,” 2002, pp. 1-12.

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