Frequency and phase correction in a phase-locked loop (PLL)

Details Frequency and phase correction in a phase-locked loop (PLL) Frequency and phase correction in a phase-locked loop (PLL)

2007-10-02

2007-10-02

Payne, David C. (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S354000, C375S371000, C375S373000

Reexamination Certificate

active

10725763

ABSTRACT:
In one embodiment, a system for frequency and phase correction in a phase-locked loop (PLL) includes a phase frequency detector, first and second charge pumps respectively generating a first current and a voltage, a voltage-to-current (V2I) converter, a current summer, and a current-controlled oscillator (CCO). The phase frequency detector detects a frequency difference and a phase difference between a clock signal and a comparison signal, communicates the frequency difference to a first charge pump generating a first current, and communicates the phase difference to a second charge pump generating a voltage. The comparison signal is derived from an output signal of the PLL. The first charge pump modifies the first current according to the frequency difference and communicates the first current to the current summer. The second charge pump modifies the voltage according to the phase difference and communicates the voltage to the V2I converter. The V2I converter generates a second current corresponding to the voltage and communicates the second current to the current summer. The current summer combines the first and second currents with each other to generate a control current for the CCO and communicates the control current to the CCO. The CCO generates one or more oscillating signals according to the first and second currents. A frequency of an oscillating signal from the CCO changes in response to the modification of the first current, and a phase of the oscillating signal changes in response to the modification of the second current.

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