Frequency adjustable PLL clock generation for a PLL based microp

Details Frequency adjustable PLL clock generation for a PLL based microp Frequency adjustable PLL clock generation for a PLL based microp

1995-02-03

1997-06-24

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

331 1R, 331177R, 327156, H03D 324

Patent

active

056423888

ABSTRACT:
A PLL based microprocessor whose frequency may be adjusted by using a microprocessor clock control circuit. The microprocessor clock control circuit comprises a circuit for providing a slew rate limited overdampened PLL that continuously seeks a new frequency, a circuit for selecting a current target frequency for the microprocessor, a circuit for comparing the current target frequency to the current frequency setting of the microprocessor, and a circuit for adjusting the current frequency setting of the microprocessor to match the current target frequency.

REFERENCES:
patent: 5493713 (1996-02-01), Horsfall et al.
patent: 5497126 (1996-03-01), Kosiec et al.
patent: 5526362 (1996-06-01), Thompson et al.

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