Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1999-09-17
2004-03-09
Chin, Stephen (Department: 2634)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S373000, C375S375000, C375S376000, C327S156000
Reexamination Certificate
active
06704381
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
The present invention may relate to application Ser. No. 09/398,936, filed concurrently, which is hereby incorporated by reference in its entirety.
FIELD OF THE INVENTION
The present invention relates to phase lock loop circuits generally and, more particularly, to frequency acquisition rate control in phase lock loop circuits.
BACKGROUND OF THE INVENTION
PLLs are generally considered clock multipliers. For example, an input reference clock having a frequency of 10 Mhz can be multiplied by the PLL to yield an output clock signal having a frequency of 200 Mhz. Ideally, this clock multiplication would result in an output clock that is in perfect phase/frequency with the reference clock. A phase frequency detector (PFD) is used to generate the proper frequency.
FIG. 1
illustrates a conventional phase lock loop circuit
10
. The circuit
10
has a phase frequency detector (PFD)
12
, a charge pump/loop filter
14
, a voltage controlled oscillator
16
and a divider
18
. The VCO
16
presents a signal to the divider
18
. The divider
18
presents a feedback signal to the PFD
12
. The PFD
12
also receives a reference clock signal CLK. The difference in frequency between the reference clock and the feedback signal is used to generate two pump signals that are presented to the charge pump/loop filter
14
. The charge pump/loop filter
14
presents a voltage control signal to the voltage controlled oscillator
16
in response to the pump signals. During normal operating conditions, the reference clock is generally synchronized with the feedback signal. Such a synchronization is shown by the block
20
.
The acquisition rate of a PLL refers to the rate (e.g., MHz/&mgr;S) that a PLL can acquire lock. The acquisition rate is measured when (i) switching from a first frequency (e.g., A) to a second frequency (e.g., B) or (ii) moving from an unlock state to lock (e.g., start-up). When frequency A is equal to frequency B, the acquisition rate refers to the rate of phase re-acquisition. A typical PLL will lose lock when switching from a reference clock A to a reference clock B. When the PLL loses lock, the output frequency can jump. A jump in frequency can cause problems in systems that are attached to the PLL.
Applications of PLLs in modern computers may require switching between reference clocks that are at about the same frequency and have some random phase difference. In order to minimize frequency jumps when switching between such reference clocks, the acquisition rate should be as low as possible.
Referring to
FIGS. 2A-C
, diagrams illustrating conventional methods of controlling the acquisition rate of a PLL are shown.
FIG. 2A
shows a circuit diagram illustrating a conventional method of reducing the acquisition rate. The acquisition rate of a PLL is reduced by using a resistor
22
and a large capacitor
24
in the loop filter. The large capacitor
24
ensures that the filter node can not change too fast in response to correctional signals from the charge pump. The large capacitor
24
requires a large die area. When switching reference clocks, a flow of current from the charge pump into the filter will result. An immediate voltage jump will appear across the resistor
22
, Ip * R, that will result in a frequency jump on the output of the VCO. The large capacitor
24
will not be able to eliminate the frequency jump.
FIG. 2B
shows a circuit diagram illustrating a conventional method of increasing the acquisition rate in a PLL. A second current source Ii is used to increase the pump current when the PLL is out of lock. The increased pump current increases the acquisition rate. The use of multiple current sources can also be applied to reduce the acquisition rate. When sensing that the PLL is out of lock, the pump current is reduced until lock is acquired. In order to reduce the acquisition rate, the charge pump current might have to drop by a large factor. Reducing the charge pump current can (i) result in the charge pump not functioning properly due to slew rate limitation, (ii) interfere with the PLL close loop response, (iii) make the PLL more susceptible to outside noise, and/or (iv) require the ability to sense a ~500 pS phase difference (that may not be practical).
FIG. 2C
shows a block diagram illustrating a conventional method of altering the acquisition rate in a PLL using a VCO gain control. Controlling the VCO gain requires an additional buffer
28
in front of the VCO. The added buffer
28
is very sensitive to noise. Altering the VCO gain can (i) interfere with the PLL close loop response and (ii) require the ability to sense a ~500 pS phase difference (that may not be practical). The frequency lock range of the PLL will be reduced if the VCO gain is set low to achieve a slow lock time.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate (i) a first reference signal in response to a pump-up signal and (ii) a second reference signal in response to a pump-down signal. The second circuit may be configured to generate (a) a first control signal in response to (i) the pump-up signal and (ii) the second reference signal and (b) a second control signal in response to (i) the pump-down signal and (ii) the first reference signal.
The objects, features and advantages of the present invention include providing an apparatus that controls the frequency acquisition rate of a PLL that may (i) not require a large filter capacitor, (ii) not alter normal PLL close loop response, (iii) not require alteration of the charge pump current, (iv) not cause the charge pump to be sensitive to noise, (v) not require decision making circuitry to decide when to turn on a lock rate control, (vi) be on all the time, (vii) not require additional buffers in front of the VCO, (viii) not affect PLL lock range, and/or (ix) work with existing PLL circuits.
REFERENCES:
patent: 4568888 (1986-02-01), Kimura et al.
patent: 4875108 (1989-10-01), Minuhin et al.
patent: 5675291 (1997-10-01), Sudjian
patent: 5805002 (1998-09-01), Ruetz
patent: 5950115 (1999-09-01), Momtaz et al.
patent: 6011822 (2000-01-01), Dreyer
patent: 6239632 (2001-05-01), Moyal et al.
Nathan Y. Moyal et al., Method, Architecture and Circuitry for Controlling the Pulse Width in a Phase and/or Frequency Detector, Ser. No. 09/398,936, filed Sep. 17, 1999.
Marlett Mark
Meyers Steve
Moyal Nathan Y.
Williams Bertrand J.
Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
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