Freezing mechanism for debugging

Details Freezing mechanism for debugging Freezing mechanism for debugging

1998-09-16

2002-05-14

Wong, Peter S. (Department: 2181)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S025000, C714S035000, C714S056000

Reexamination Certificate

active

06389557

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to data communication, and more particularly, to a system for freezing a data communication device to provide a debugging procedure.
BACKGROUND ART
Subtle errors may degrade performance of a communication device and reduce its efficiency without completely shutting down any portion of the device. Therefore, it would be desirable to provide a communication device having a debug mode that enables a diagnostician to stop or freeze the device in a desired state in order to locate errors.
The causes of errors can lie in many different device components. Also, communications problems can be random and troublesome to reproduce. Therefore, it would be desirable to provide a freezing mechanism that allows a communication device to be monitored in various states so as to recreate an event that may be hard to capture during actual operation of the device.
DISCLOSURE OF THE INVENTION
Accordingly, an advantage of the present invention is in providing a communication device having a debug mode that enables a diagnostician to stop or freeze the device in a desired state in order to locate errors.
Another advantage of the present invention is in providing a freezing mechanism that allows a communication device to be monitored in various states so as to recreate an event that may be hard to capture during actual operation of the device.
These and other advantages of the invention are achieved at least in part by providing a debugging system having an internal clock generating circuit responsive to an external clock signal for producing an internal clock signal supplied to internal circuitry of a data processing device. A freezing circuit supplied with a stop signal fixes the internal clock signal in an off state to freeze operation of the internal circuitry. A bypass circuit supplied with a bypass clock signal controls the internal clock signal in accordance with the bypass clock signal.
The debugging system may comprise a bypass mode control circuit supplied with a bypass mode control signal. The internal clock signal is controlled in accordance with the bypass clock signal when the bypass mode control signal is in a first state. However, the internal clock signal is controlled in accordance with the external clock signal when the bypass mode control signal is in a second state.
In accordance with one aspect of the invention, a system for testing a data processing device may comprise a gate circuit responsive to an external clock signal for producing an internal clock signal supplied to internal circuitry of the device. The gate circuit may also receive a freezing signal produced by a freezing circuit in response to a stop signal to set the internal clock signal into an inactive state.
A multiplexer coupled to the gate circuit and controlled by a bypass mode control signal may allow the internal clock signal to pass to the internal circuitry when the bypass mode control signal is in an inactive state. Also, the multiplexer receives a bypass clock signal allowed to pass to the internal circuitry when the bypass mode control signal is in an active state.
In accordance with a preferred embodiment of the invention, the freezing circuit may comprise a first flip-flop having a data input supplied with the stop signal, and a clock input supplied with the external clock signal. A data input of a second flip-flop may be coupled to an output of the first flip flop. A clock input of the second flip-flop may be supplied with the external clock signal.
The gate circuit may have a first input supplied with the external clock signal, and a second input coupled to an output of the second flip-flop. The multiplexer may have a first input coupled to the output of the gate circuit, and a second input supplied with the bypass clock signal.
In accordance with a method of the present invention, the following steps are carried out for testing a data processing device:
producing an internal clock signal for the device in response to an external clock signal, and
supplying a stop signal to set the internal clock signal into an off state to freeze the operation of the device.
A bypass clock signal may be supplied to control the internal clock signal when the operation of the device is frozen.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.


REFERENCES:
patent: 4628511 (1986-12-01), Stitzlein et al.
patent: 4669079 (1987-05-01), Blum
patent: 4852095 (1989-07-01), Meltzer
patent: 5668983 (1997-09-01), Houle et al.
patent: 6014752 (2000-01-01), Hao et al.
patent: 6047321 (2000-04-01), Rabb et al.
patent: 6122762 (2000-09-01), Kim

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