Computer graphics processing and selective visual display system – Computer graphics display memory system – Addressing
Reexamination Certificate
1998-11-05
2001-09-11
Tung, Kee M. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Addressing
C345S536000
Reexamination Certificate
active
06288731
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an image processing apparatus and an image processing method and, more particularly, to an image processing apparatus and an image processing method in which a function is performed to freely deform a two-dimensional image data.
2. Description of the Related Art
Conventionally a two-dimensional graphic is displayed in a definite form. However, the need of free deformation of the two-dimensional graphic is increased in conjunction with a technical development with regard to a graphic process.
FIG. 1
is a block diagram showing the structure of a conventional two-dimensional image processing apparatus. The two-dimensional image processing apparatus is composed of a CPU
11
, and a two-dimensional (2D) graphic processor
12
connected to the CPU
11
. A figure ROM
13
and a display buffer section
14
are connected to the 2D graphic processor
12
. The 2D graphic processor
12
is composed of a DATA I/F section
15
, an object table section (hereinafter, to be referred to as an OBJ table section)
16
, an FI/FO section
17
composed of first-in first-out registers, a timing signal generating section
19
, a ROM address adder
20
, a ROM address generating counter
21
and a display buffer section address adder
22
.
FIG. 2
is a flowchart showing an operation of the conventional two-dimensional image processing apparatus. When the CPU
11
sends a CPU data signal S
3
to the DATA I/F section
15
, the DATA I/F section
15
outputs an OBJ table section setting data signal S
4
to the OBJ table
16
to set a record of display parameters of respective figures (Step S
1
), if the CPU data signal S
3
is a signal to be directed to the OBJ table
16
. An X coordinate origin value P1, a Y coordinate origin value P2 and a display figure ROM origin value P3 are given as the display parameters of the OBJ table
16
. On the other hand, the DATA I/F section
15
outputs an FI/FO setting data signal S
5
to the FI/FO section
17
to set OBJ addresses PA included in the signal S
5
, if the CPU data signal S
3
is a signal to be directed to the FI/FO section
17
.
The FI/FO section
17
switches an FI/FO section empty signal S
8
directed to the timing signal generating section
19
from a disable state to an enable state at a time point when the OBJ addresses PA are set therein. Accordingly, the timing signal generating section
19
is initialized to be set to a drawing state. In this state, the timing signal generating section
19
and the display buffer section
14
are set to an active state in response to a vertical synchronous signal S
1
. At that time, if the FI/FO section empty signal S
8
is in the disable state, the 2D graphic processor
12
does not operate until a next horizontal synchronization signal S
2
is inputted. If the FI/FO section empty signal S
8
is in the enable state, when the timing signal generating section
19
outputs an FI/FO section request signal S
7
to the FI/FO section
17
in response to the horizontal synchronous signal. The FI/FO section
17
outputs an OBJ table section address signal S
6
to the OBJ table
16
in response to the FI/FO section request signal S
7
to read out the parameters of the figure data to be displayed (Steps ST
2
to ST
4
).
After the respective parameters of the figure data are outputted from the OBJ table
16
, the timing signal generating section
19
outputs a ROM calculation control signal S
21
to the ROM address generating counter
21
. The ROM address generating counter
21
receives the ROM calculation control signal S
21
as a start signal, and then generates and outputs a ROM address generating counter output signal S
13
. On the other hand, the ROM address adder
20
adds the ROM address generating counter output signal S
13
and the display figure ROM origin value P3 included in a figure ROM address origin signal S
11
supplied from the OBJ table
16
to generate and output a figure ROM address signal S
12
to the figure ROM
13
(Step S
5
).
The figure ROM
13
outputs a display buffer section data signal S
15
having a desired figure data to the display buffer section
14
based on the figure ROM address signal S
12
. At the same time, the display buffer section address adder
22
adds the ROM address generating counter output signal S
13
and each of the X coordinate origin value P1 included in an X coordinate origin signal S
9
supplied from the OBJ table
16
and the Y coordinate origin value P2 included in a Y coordinate origin signal S
10
to determine a display position where the figure is to be displayed, and then outputs a generated display buffer section address signal S
17
to the display buffer section
14
.
While the display buffer section data signal S
15
and the display buffer section address signal S
17
are outputted, a display buffer enable signal S
16
supplied from the ROM address generating counter
21
is switched from the disable state to the enable state. Thus, the figure data is stored in the display buffer section
14
in accordance with the display positions of the figure data.
The timing signal generating section
19
determines the state of the FI/FO section empty signal S
8
sent from the FI/FO section
17
. The timing signal generating section
19
repeats this operation until this signal S
8
is switched to the disable state. Also, the figure data sent from the figure ROM
13
is stored in the display buffer section
14
. At a time point when all the pixel data of a single figure for the horizontal line is stored in the display buffer section
14
, the display buffer enable signal S
16
is switched from the enable state to the disable state. Thus, the operation for the horizontal line is ended (Step ST
6
). The above operation is repeated for all the horizontal lines.
Next, all the data stored in the display buffer section
14
are outputted to a display device (not shown). Through the repetition of the above mentioned operation, the figure data can be displayed on the screen.
A procedure when a display figure example 1 (sp
1
) and a display figure example 2 (sp
2
) are set to be displayed on the screen as a display screen example 1 (SC
1
), and the display figure examples
1
and
2
are deformed as shown as a display screen example 2 (SC
2
), a display screen example 3 (SC
3
) and a display screen example
4
(SC
4
) in this order will be described below.
FIGS. 3A
to
3
D show the display figure example 1 (sp
1
) on the coordinates (x1,y1) of the display screen and the display figure example 2 (sp
2
) on the coordinates (x2,y2).
FIG. 4
is a schematic diagram showing the content of a conventional figure ROM mapping.
In a display screen example 1 (SC
1
) of
FIG. 3A
, a figure ROM data
1
(RD
1
) mapped into an address R1(h) of the figure ROM
13
shown in
FIG. 4
is displayed as a display figure example 1 (sp
1
), and a figure ROM data
2
(RD
2
) mapped into an address R2(h) is also displayed as a display figure example 2 (sp
2
). For example, when the respective parameters of the display figure example 1 (sp
1
) are to be set in an address a(h) of the OBJ table
16
, the CPU
11
sets x1(h) to the X coordinate origin value P1, y1(h) to the Y coordinate origin value P2, and R1(h) to the display figure ROM origin value P3, respectively. Also, when the respective parameters of the display figure example 2 (sp
2
) are set in an address b(h) of the OBJ table
16
, the CPU
11
sets x2(h) to the X coordinate origin value P1, y2(h) to the Y coordinate origin value P2 and R2(h) in the display figure ROM origin value P3, respectively. Moreover, the CPU
11
sets the addresses a(h) and b(h) of the OBJ table
16
to the FI/FO section
17
. Thus, the display screen example 1 (SC
1
) can be displayed on the screen through the above mentioned operation.
When the display figure example 1 and the display figure example 2 are deformed as shown as the display screen example 2 (SC
2
) in
FIG. 3B
, the figure ROM data
3
(RD
3
) is mapped into an address R3(h) of the figure ROM
13
, and the figure ROM data
NEC Corporation
Scully Scott Murphy & Presser
Tung Kee M.
LandOfFree
Free deformation of image data does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Free deformation of image data, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Free deformation of image data will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2438450