Electrical computers and digital data processing systems: input/ – Intrasystem connection
Reexamination Certificate
1999-02-22
2001-08-14
Dharia, Rupal (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
C707S793000, C707S793000, C707S793000, C707S793000, C707S793000, C341S050000, C341S055000, C341S067000, C341S106000
Reexamination Certificate
active
06275880
ABSTRACT:
INTRODUCTION TO THE INVENTION
The present invention relates to the transmission of data, for example from one network device to another, over a link, which may be of substantial length, in a multiplicity of parallel lines. The invention is particularly, although not necessarily exclusively, intended for use in systems where the data rate is very high, for example substantially in excess of one hundred megabits per second.
BACKGROUND TO THE INVENTION
The present invention is particularly intended for use in a system wherein data is conveyed in a multiplicity, such as eight, serial data streams on corresponding parallel lines so that the data lines constitute a synchronous parallel bus. For example, such a parallel bus may be employed for the transmission of data from one device or ‘chip’ to another, a relatively wide parallel signal being converted group by group into corresponding serial groups which are transmitted on the respective lines of the synchronous parallel bus. In a particular example, the parallel digital signal may be sixty-four bits wide and each eight-bit group (i.e. byte) in the digital signal may be serialised and transmitted along a respective one of the lines of the parallel bus. At the receiver, or destination ‘chip’, the serial groups may be deserialised to reconstitute the data signal in its original wide parallel form.
Systems of this nature, and intended to deal with the problems of phase shift and byte alignment, are the subject of the above-mentioned earlier patent applications which are commonly assigned and are incorporated herein by reference.
High-speed serial links normally employ framing codes with redundancy, such as schemes known as 8B/10B, and also include cyclic redundancy codes for the detection of transmission errors. The main disadvantages of these schemes are the substantial transmission capacity (i.e. bandwidth) that they require. Furthermore, the complexities of implementing redundant encoders at very high operating frequencies are substantial.
The present invention is based on the use of an additional line, herein called a ‘control line’, in parallel with the high-speed parallel bus. Such a control line has a general utility, for example for the transmission of training patterns which may be employed, as suggested in the earlier applications, to maintain the data lines in synchronism. The object of the present invention is to provide framing codes on such a control line in a manner which employs a high degree of redundancy to provide error detection and preferably includes a parity check, so that coding redundancy or cyclic redundancy code protection in the data signal is not required, the corresponding bandwidth being saved.
BRIEF SUMMARY OF THE INVENTION
Broadly, the invention resides in a method of transmitting data wherein serial data streams are transmitted on parallel lines at a common frequency, in groups of symbols, and a framing signal is transmitted on an additional parallel line, the framing signal being composed of groups of symbols corresponding to the groups of data symbols, each group of the framing signal comprising a majority of symbols capable of representing a first plurality of code words of which only a second plurality, very much smaller than the first plurality, are defined valid code words, and a minority of symbols indicating a parity check.
The serial data streams may be obtained by the conversion of a parallel digital signal into a plurality of serial signals wherein each group of symbols in each serial signal corresponds to a group of symbols in the parallel digital signal.
Preferably, each valid code word in a group of symbols in the framing signal consists of a first sub-group of similar symbols and a second sub-group of similar symbols. Such a particular choice enables the provision of four valid sub-codes, according as the sub-groups of symbols are similar or different. In any event, the number of possible codes is an exponential function of the number of symbols in the two sub-groups and will be much greater than the valid code words. In a particular example, wherein each group of symbols consists of eight binary digits, the framing code words consist of two groups of three digits and there are only four valid code words out of the sixty-four possible code words which may be made from the six digits.
A minority, in a specific example two symbols out of eight, of the symbols of the framing codes may be used to provide a parity check. This parity check may be generated from the data groups but may also be generated from the data groups and the framing codes words.
Preferably, the valid code words each correspond to a specified state of the data groups, and in particular they represent the start of a data block (i.e. packet), valid data, a gap between data groups and an idle state. For valid transmission of data, these groups must occur in a valid sequence and accordingly a state machine organized in accordance with the sequence may be arranged in the receiver to track the sequence and to detect illegal sequences without requiring the intervention of a central processing unit.
Further features and advantages of the invention will become apparent from the following detailed description of a specific example.
REFERENCES:
patent: 5313203 (1994-05-01), Suu et al.
patent: 5999934 (1999-12-01), Cohen et al.
patent: 2 336 075 (1999-10-01), None
patent: 2 336 074 (1999-10-01), None
patent: 2343092A (2000-04-01), None
Butler J. Noel
Cremin Con
Fanning Neil O.
Hughes Mark A.
O'Neill Eugene
3Com Technologies
Dharia Rupal
Nixon & Vanderhye P.C.
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