Framework for high-performance hardware abstraction

Details Framework for high-performance hardware abstraction Framework for high-performance hardware abstraction

2007-09-04

2007-09-04

Sparks, Donald (Department: 2181)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C719S327000, C719S321000

Reexamination Certificate

active

10656587

ABSTRACT:
In some embodiments, a system comprises a processor that executes an algorithm. Coupled to the processor is memory that stores the algorithm. In addition, the system comprises a hardware unit that is generally not accessible to the algorithm and an abstraction layer that indirectly facilitates interaction between the hardware unit and the algorithm. The hardware unit comprises one or more physical resources, such as data channels, that are associated by the abstraction layer with a logical resource. In addition, the abstraction layer creates an identifier to the logical resource that may be used by the algorithm. Associated with the identifier is a private state that represents the most recently configured settings of the logical resource. A vector table is used in conjugation with the private state to identify memory locations of optimized command functions that carry out operations associated with the hardware unit. In addition, the vector table is adapted to reflect the run-time state of the system.

REFERENCES:
patent: 6941390 (2005-09-01), Odom
patent: 6959439 (2005-10-01), Boike
patent: 2003/0233487 (2003-12-01), Ruget et al.
“Design and Implementation of an eXpressDSP-Compliant DMA Manager for C6XIX”, Karaorman et al, Texas Instruments Application Report, Sep. 2002.

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