Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1997-12-31
2001-03-20
Ton, Dang (Department: 2661)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S421000, C370S462000, C370S395430
Reexamination Certificate
active
06205152
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to frame relay and ATM communications and, more specifically, to a traffic management interface for converting frame relay traffic to ATM traffic using an ASIC circuit for implementing a leaky bucket algorithm.
BACKGROUND OF THE INVENTION
Information systems have evolved from centralized mainframe computer systems supporting a large number of users to distributed computer systems based on local area network (LAN) architectures. As the cost-to-processing-power ratios for desktop PCs and network servers have dropped precipitously, LAN systems have proved to be highly cost effective. As a result, the number of LANs and LAN-based applications has exploded.
A consequential development relating to the increased popularity of LANs has been the interconnection of remote LANs, computers, and other equipment into wide area networks (WANs) in order to make more resources available to users. However, a LAN backbone can transmit data between users at high bandwidth rates for only relatively short distances. In order to interconnect devices across large distances, different communication protocols have been developed. These include X.25, ISDN, and frame relay, among others.
Most data transmissions, including file transfers and voice, occur in bursts at random intervals. The bursty nature of most data transmissions means that if the bandwidth allocated to a transmitting device is determined according to its peak demand, much bandwidth is wasted during the “silences” between data bursts. This variable bandwidth demand problem has been solved in part by X.25 and frame relay, which use statistical multiplexing to improve the throughput of multiple users. Statistical multiplexing takes advantage of the bursty nature of data transmissions to allow a user to transmit bursts of data in excess of the user's allocated bandwidth for relatively short periods of time.
Frame relay has proved to be one of the most popular communication protocols. Frame relay provides up to T
3
level speeds (from 56 Kbps up to about 45 Mbps) using packet switching technology. It is optimized for the transfer of protocol-oriented data in packets of variable length. Data is sent in high-level data link control packets, called “frames”. A typical frame includes a “header”, comprising an address block and a control block, a “payload” or data block that is the actual data to be transferred from endpoint to endpoint, and a CRC error correction block.
An end user transmits data according to a committed information rate (CIR) and a maximum burst size. Bandwidth is allocated dynamically on a packet-by-packet basis within the network. If the end user exceeds the CIR for a short period of time, the transmitted data is buffered within the frame relay network for later transmission. If this condition persists, however, traffic policing and congestion control mechanisms in the network, reduce the rate at which the end user transmits data.
Frame relay frames have only a small amount of “overhead” (i.e., header and CRC), only seven (7) bytes compared to hundreds of data bytes). However, the variable lengths of the payload cause variable length delays as the frames move through the network switches. This makes frame relay suitable to pure data transfers, but less suitable to the transfer of mixed voice, data and video. Additionally, the newest LAN/WAN applications, including file transfers, imaging, video conferencing, and the like, demand great amounts of bandwidth that cannot be serviced by frame relay.
ATM is a relatively new technology and currently represents only a comparatively small percentage of the installed network infrastructure. Frame relay still remains as a dominant portion of the installed network infrastructure. Additionally, since many information systems may never need video or other high bandwidth applications, it is unlikely that every LAN or WAN system will need to be converted to an ATM system. Hence, frame relay and ATM will likely coexist for a long period of time.
In order to allow frame relay systems and ATM systems to communicate with one another, a host of well-known interfaces have been developed to interconnect frame relay based networks with ATM based networks. These frame relay-to-ATM interfaces typically include a high-level data link control (HDLC) interface for sending and receiving frames from a frame relay-based network and a segmentation and reassembly (SAR) interface for sending and receiving cells from an ATM-based network. Between the HDLC and the SAR, a memory holds the payloads of the frames and/or cells, and a traffic control processor monitors the traffic for every connection and adjusts the traffic flow based on a leaky bucket software routine. The traffic control processor also provides the frame switching and forwarding functions for every connection.
However, the prior art frame relay-to-ATM interfaces are limited by the processing capabilities of the traffic control processor and the memory used to store the cell and frame payloads. The traffic control processor performs a traffic policing algorithm for every connection. As the number of connections grows, the traffic control processor consumes larger amounts of processing power for traffic policing. For comparatively large frames, the traffic control processor can read the frame header information and implement the leaky bucket algorithm for each frame received from a user. However, as large numbers of comparatively small frames are received, the processor spend an increasingly large amount of time reading header information and implementing traffic flow calculations.
Furthermore, the traffic control processor and payload memory are typically coupled to the HDLC and the SAR by a common bus. The foreground tasks executed by the traffic control processor, such as implementing the leaky bucket algorithm, must therefore be stalled while frame payloads and cell payloads are stored in the payload memory by the HDLC and the SAR. A similar problem occurs when ATM cells must be reassembled into a large number of comparatively small frames.
The end result is that the traffic control processor frequently cannot keep up with data traffic and the performance of the frame relay-to-ATM interface deteriorates. Consequently, at least part of the data traffic frequently must be re-transmitted in order to complete the transfer.
There is therefore a need in the art for an improved frame relay-to-ATM interface capable of processing a large volume of data traffic with minimal deterioration in performance. In particular, there is a need for an improved frame relay-to-ATM interface that minimizes the amount of processing performed by the traffic control processor. More particularly, there is a need for an improved frame relay-to-ATM interface that implements a traffic policing and congestion control algorithm, such as a leaky bucket algorithm, using a minimal amount of traffic control processor time.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide, for use in a processing network containing a first node operable to transmit and receive frame relay data and a second node operable to transmit and receive asynchronous transfer mode (ATM) data, a network interface for converting the frame relay data to ATM data comprising: 1) a frame relay interface circuit operable to receive the frame relay data from the first node; 2) an ATM interface circuit operable to transmit the ATM data to the second node; 3) a data bus for coupling the frame relay interface circuit and the ATM interface circuit, the data bus operable to transfer frame payload data from the frame relay interface circuit to the ATM interface circuit; 4) a data traffic controller operable to receive frame header data from the frame relay interface circuit and control transfers of the frame payload data from the frame relay interface circuit to the ATM interface circuit; and 5) a bridge for coupling the data traffic controller t
Sreedharan Sreejith
Von Ahnen Michael J.
Han John C.
Samsung Electronics Co,. Ltd.
Ton Anthony
Ton Dang
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