Computer graphics processing and selective visual display system – Computer graphics display memory system – Plural storage devices
Reexamination Certificate
2001-12-12
2004-12-21
Chauhan, Ulka J. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Plural storage devices
C345S545000, C345S574000, C345S570000
Reexamination Certificate
active
06833834
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to graphics systems and, more particularly, to the organization and reordering of display information in the frame buffer.
2. Description of the Related Art
A computer system typically relies upon its graphics system for producing visual output on the computer screen or display device. Early graphics systems were only responsible for taking what the processor produced as output and displaying it on the screen. In essence, they acted as simple translators or interfaces. Modem graphics systems, however, incorporate graphics processors with a great deal of processing power. They now act more like coprocessors rather than simple translators. This change is due to the recent increase in both the complexity and amount of data being sent to the display device. For example, modern computer displays have many more pixels, greater color depth, and are able to display more complex images with higher refresh rates than earlier models. Similarly, the images displayed are now more complex and may involve advanced techniques such as anti-aliasing and texture mapping.
As a result, without considerable processing power in the graphics system, the CPU would spend a great deal of time performing graphics calculations. This could rob the computer system of the processing power needed for performing other tasks associated with program execution and thereby dramatically reduce overall system performance. With a powerful graphics system, however, when the CPU is instructed to draw a box on the screen, the CPU is freed from having to compute the position and color of each pixel. Instead, the CPU may send a request to the video card stating, “draw a box at these coordinates.” The graphics system then draws the box, freeing the processor to perform other tasks.
Generally, a graphics system in a computer is a type of video adapter that contains its own processor to boost performance levels. These processors are specialized for computing graphical transformations, so they tend to achieve better results than the general-purpose CPU used by the computer system. In addition, they free up the computer's CPU to execute other commands while the graphics system is handling graphics computations. The popularity of graphics applications, and especially multimedia applications, has made high performance graphics systems a common feature in many new computer systems. Most computer manufacturers now bundle a high performance graphics system with their computing systems.
In many applications, it may be useful to have two monitors or displays connected to the same computer system. For example, in some graphical editing applications, it is desirable to use one monitor to show a close-up of an area being edited, while another monitor shows a wider field of view of the object or picture being edited. Alternatively, some users may configure one monitor to display the object being edited and the other monitor to display various palettes or editing options that can be used while editing. Another situation where multiple displays are useful occurs when several users are connected to a single computer. In such a situation, it may be desirable for each user to have their own display. In another situation, it may simply be desirable to have multiple displays that each display a different portion of an image in order to provide a larger display than would otherwise be possible. Another example is stereo goggles, which present different images to their wearer's left and right eyes in order to create a stereo viewing effect. These examples illustrate just a few of the many situations where it is useful to have multiple displays connected to the same computer system.
Given the complexity and expense of many graphics systems, it may be desirable to provide a graphics system that can support multiple displays without duplicating the entire graphics system. Thus, there is a need to be able to share portions of a graphics system between multiple display channels.
SUMMARY
Various embodiments of a graphics system and method for reordering pixels output from a frame buffer are disclosed. In one embodiment, the graphics system may include a frame buffer, a write address generator, and a pixel buffer. The frame buffer is configured to output pixels, but the pixels may not be output in display order. For example, the frame buffer may be configured so that pixels may be more efficiently written into the frame buffer (e.g., based on the arrangement of interleaves within the frame buffer and the input configuration of the frame buffer). The pixels may be stored in the frame buffer in a way that makes it inefficient to read them from the frame buffer in display order. Accordingly, pixels may be output from the frame buffer in an order other than display order. The write address generator may be configured to calculate a write address for each pixel output by the frame buffer. Each write address corresponds to a relative display order of a respective pixel. The pixel buffer is coupled to store the pixels output by the frame buffer at the write addresses calculated by the write address generator.
In some embodiments, the graphics system may be configured to output the pixels in bursts. The pixel buffer may include multiple partitions, and each partition may be configured to store at least one burst of pixels for a respective display channel. The write address generator may include a base address generator, which may generate the same base address for all of the pixels output in a first burst, and an offset address generator, which may generate an offset for each pixel that corresponds to each pixel's relative display order within the first burst. The write address generator may be configured to concatenate the base address and the offset to produce the write address. By storing the pixels at their respective write addresses, the pixels received in each burst may be stored in display order within the pixel buffer.
In some embodiments the write address generator may be configured to calculate write addresses for the pixels so that the pixels in a first burst are stored in at least one block in the pixel buffer. The write address generator may be configured to store each display channel's blocks of pixels in any unallocated blocks in the pixel buffer. The write address generator may also be configured to track those blocks in the pixel buffer that are already allocated, which display channel each allocated block is storing pixels for, and the relative display order of the blocks storing pixels for each display channel.
In some embodiments of the graphics system, the frame buffer may include one or more 3D-RAM memory devices, multiple memory banks, and/or multiple interleaves.
In alternative embodiments, the graphics system may include a frame buffer, a read address generator, and a pixel buffer. The frame buffer may not output pixels in display order. Pixels output from the frame buffer may be stored in the pixel buffer in the order they are read from the frame buffer. A read address generator may calculate a read address for each pixel stored in the pixel buffer. Each read address corresponds to a relative display order of a respective pixel. Successively generated read addresses access pixels in the pixel buffer in display order.
REFERENCES:
patent: 5544306 (1996-08-01), Deering et al.
patent: 5796412 (1998-08-01), Kim
patent: 5945997 (1999-08-01), Zhao et al.
patent: 6310657 (2001-10-01), Chauvel et al.
patent: 6323868 (2001-11-01), Paluch et al.
patent: 6496192 (2002-12-01), Shreesha et al.
patent: 2003/0016302 (2003-01-01), Fudge et al.
3D-RAM Spec 8 Press Release dated May 20, 1997, 2 pages.
3D-RAM Spec www.mitsubishichips.com/data/datasheets/memory/mempdf/ds/c99001.pdf, (date Aug. 1996 given in press release, see A3), 170 pages.
Pacifica RAMDAC spec BT497/8 from Brooktree, Feb. 1996, 53 pages.
“Sun™ Elite3D Frame Lock and Buffer Swap Synchronization Installation Guide”, Aug. 1999, 42 pages.
Kehlet David C.
Kubalska Ewa M.
Lavelle Michael G.
Tang Yan Yan
Wasserman Michael A.
Chauhan Ulka J.
Hood Jeffrey C.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Sun Microsystems Inc.
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