Frame buffer memory system for reducing page misses when renderi

Details Frame buffer memory system for reducing page misses when renderi Frame buffer memory system for reducing page misses when renderi

1998-04-01

2000-07-18

Tung, Kee M.

Computer graphics processing and selective visual display system

Computer graphic processing system

Plural graphics processors

345515, 345422, 345 1, G09G 536

Patent

active

060914289

ABSTRACT:
In a computer image generation system, a method for reducing page switches when rendering polygons to a color and Z-buffer using a memory subsystem with N banks of memory. The method is performed by first allocating the pages of a first memory subsystem (Z-buffer or color) to consecutive and contiguous pages of the frame buffer memory, where the individual frame buffer memory pages reside in one of N banks of memory. The second memory subsystem(Z-buffer or color)is then allocated according to the following rule: the allocation of the second memory subsystem is made such that its first page does not reside in a memory bank whose index is equal to the index of the memory bank allocated to the first page of the memory subsystem. The allocation rule effectively reduces page switches by virtue of being able to access different memory banks for both Z-buffer and color read and writes thereby by avoiding the computational costs associated with opening multiple memory pages in the same memory bank.

REFERENCES:
patent: 5758045 (1998-05-01), Moon et al.
patent: 5937204 (1999-08-01), Schinnerer
patent: 5945997 (1999-08-01), Zhao et al.

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