Fragment storage for data alignment and merger

Details Fragment storage for data alignment and merger Fragment storage for data alignment and merger

2007-07-10

2007-07-10

Park, Ilwoo (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Peripheral adapting

C710S307000, C710S052000

Reexamination Certificate

active

10685129

ABSTRACT:
A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a packet data transfer circuit that uses a fragment storage buffer to align and/or merge data being transferred to or from memory on a plurality of channels. In a packet reception embodiment, a data shifter and fragment store buffer are used to align received packet data to any required offset. The aligned data may and then be written to the system bus or combined with data fragments from prior data cycles before being written to the system bus. When packet data is being transferred to memory on a plurality of channels, the fragment storage may be channelized using register files or flip-flops to store intermediate values of packets and states for each channel.

REFERENCES:
patent: 6188699 (2001-02-01), Lang et al.
patent: 6414609 (2002-07-01), Zukawa et al.
patent: 2004/0034828 (2004-02-01), Hocevar
C. D. Cranor et al., “Architectural Considerations for CPU and Network Interface Integration,” http://chuck.cranor.org/p/unum—hoti99.pdf, printed Feb. 15, 2005.
C.D. Cranor et al. “Architectural Considerations for CPU and Network Interface Integration,” http://chuck.cranor.org/p/unum—slides—hoti99.pdf, printed Feb. 15, 2005.
C.D. Cranor et al., “Architectural Considerations for CPU and Network Interface Integration,” IEEE Micro Chips, Systems, Software, and Applications, Jan./Feb. 2000, pp. 18-26.

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