Fragment processor having dual mode register file

Details Fragment processor having dual mode register file Fragment processor having dual mode register file

2004-12-10

2010-10-26

Hsu, Joni (Department: 2628)

Computer graphics processing and selective visual display system

Computer graphics display memory system

Register

C345S506000, C345S502000

Reexamination Certificate

active

07821520

ABSTRACT:
A new, useful, and non-obvious shader processor architecture having a shader register file that acts both as an internal storage register file for temporarily storing data within the shader processor and as a First-In First-Out (FIFO) buffer for a subsequent module. Some embodiments include automatic, programmable hardware conversion between numeric formats, for example, between floating point data and fixed point data.

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Eggers, et al. “Simultaneous Multithreading: A Platform for Next-Generation Processors,” IEEE Micro, vol. 17, No. 5, pp. 12-19, Sep./Oct. 1997.

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