Fractional-N synthesizer and method of programming the...

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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C375S373000, C375S327000, C327S156000, C331S00100A, C331S025000

Reexamination Certificate

active

07463710

ABSTRACT:
A fractional-N synthesizer with programmable output phase including a phase locked loop having an output signal whose frequency is a fractional multiple of an input reference signal, the phase locked loop including a frequency divider. A synchronization circuit responsive to the input reference signal for generating synchronization pulses at integer multiples of M periods of the input reference signal. An interpolator is responsive to F and M, where F is the fractional value and M is the modulus, to provide to the frequency divider an output which is a fractional value equal to, on average, the input fraction. A phase adjustment circuit is responsive to the synchronization circuit for varying the phase of the output signal with respect to the input reference signal.

REFERENCES:
patent: 6353649 (2002-03-01), Bockleman et al.
patent: 6556086 (2003-04-01), Keaveney et al.
patent: 6600378 (2003-07-01), Patana
patent: 6614319 (2003-09-01), Saeki et al.
patent: 6621317 (2003-09-01), Saeki
patent: 6642800 (2003-11-01), Drapkin et al.
patent: 2002/0191727 (2002-12-01), Staszewski et al.

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