Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2001-08-29
2003-04-22
Bocure, Tesfaldet (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S375000, C327S156000, C327S157000
Reexamination Certificate
active
06553089
ABSTRACT:
1. Field of the Invention
The present apparatus and method can be used for any system that requires fractional resolution of a reference frequency, and relates, in particular, to a PLL-based frequency synthesizer for use in a modern wireless or wired communication system.
2. Background of the Related Art
Frequency synthesizers are typically used in modern wireless communication systems to produce a desired output frequency in both the receiver and transmitter. Among the various phase locked loop (PLL) based frequency synthesizers, fractional-N frequency synthesizers are suitable for the communication systems where the channel interval is small. Fractional-N architecture allows frequency resolution that is a fractional portion of a reference frequency F
REF
, and an output frequency signal F
OUT
is related to the reference frequency F
REF
by the relationship F
OUT
=F
REF
(N+K/F), where F is the fractional resolution of the device with respect to the reference frequency. The technique of fractional-N architecture requires generating a divider that is a fractional number rather than an integer. This is performed by changing the divider in the loop dynamically between the values N and N+1. If out of F cycles, division by N+1 is done K times and by N, F−K times, then the average division ratio is N+K/F.
The advantage of the fractional-N architecture is that the reference frequency F
REF
is not restricted by the channel spacing, and loop bandwidth can be increased. Therefore, phase noise and locking time is reduced. However, the switching of the divisors causes spurious signals in the synthesized output frequency signal F
OUT
. These subharmonic spurs, also referred to as fractional spurs, must be kept below some maximum acceptable limit.
FIG. 1
shows a schematic diagram of a related art fractional compensation circuit
100
, that attempts to reduce unwanted spurious signals. As shown in
FIG. 1
, a reference frequency (F
REF
)
102
, is fed into a reference frequency divider
104
, and an output
106
, of the reference frequency divider
104
, is fed into a phase detector
110
. The terms “phase detector” and “PD” refer to the same type of circuit and are used interchangeably herein. “PD
1
” and “PD
2
” are sometimes used where more than phase detector circuit is referenced. The phase detector
110
, also receives an output
108
, of a modulus divider
132
. An output
112
, of the phase detector
110
, is fed into an adder
118
. A digital to analog converter (DAC)
114
, feeds a compensation current
116
that is proportional to the fractional error phase into the adder
118
. An output
120
of the adder
118
is fed into a loop filter
122
, and an output
124
of the loop filter
122
is fed into a voltage controlled oscillator
126
. The terms “voltage controlled oscillator” and VCO refer to the same type of circuit and are used interchangeably herein. The output of the voltage controlled oscillator
126
is an F
OUT
output
128
of the fractional compensation circuit
100
, and an input to the modulus divider
132
. An accumulator
134
, has a first output
136
, fed into the modulus divider
132
and a second output
138
, fed into the digital to analog converter
114
. For proper fractional compensation, the area of the compensation pulse must be equal to the area of the main charge pump fractional-N ripple. In the related art fractional compensation circuit
100
, however, the amount of the compensation current
116
is statically fixed. Therefore, the spurious signal cancellation cannot track the dynamic change of the spurious signals with time, process, and temperature.
FIG. 2
is a schematic diagram of another related art fractional compensation circuit
200
, typically known as a fractional-N synthesizer, which controls the dividing ratio by using a sigma-delta (&Sgr;&Dgr;) modulator. As shown in
FIG. 2
, a reference frequency
202
, is fed into a reference frequency divider
204
, and an output
206
of the reference frequency divider
204
is fed into a phase detector
210
. An output
212
of the phase detector
210
is fed into a loop filter
214
, and an output
216
of the loop filter
214
is fed into a voltage controlled oscillator
218
. An output
220
of the voltage controlled oscillator
218
is a frequency output (F
OUT
)
220
of the fractional-N synthesizer, and is also input to a modulus divider
224
. The modulus divider
224
, also receives an output signal
226
, from a &Sgr;&Dgr; modulator
228
. An output
208
of the modulus divider is received by the phase detector
210
. The fractional spurious frequencies or phase noise are distributed throughout the frequency spectrum by the operation of the sigma-delta modulator. However, the absolute noise level may be increased above acceptable levels. A more robust and reliable fractional compensation scheme, which does not degrade the spectral purity, is needed.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
An object of the present invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Another object of the present invention is to provide a phase locked loop-based fractional-N synthesizer.
Another object of the present invention is to provide a fractional compensation circuit and method that incorporates two phase detectors.
Another object of the present invention is to incorporate fractional spur compensation circuitry that dynamically compensates charge pump ripple whenever the charge pump operates.
Another object of the present invention is to provide a phase locked loop-based fractional-N synthesizer and method that uses a plurality of phase detectors to dynamically cancel spurious signals.
Another object of the present invention is to provide a phase locked loop-based fractional-N synthesizer that variously delays at least one output of a plurality of phase detectors to reduce fractional spurs.
Another object of the present invention is to provide a fractional compensation circuit that uses a charge pump stage composed of N charge pumps so that a number of the N charge pumps that operate during a phase comparison is determined by a fractional accumulator stage.
An advantage of a fractional-N architecture and method according to the present invention is that a reference frequency is not restricted by the channel spacing and loop bandwidths can be increased.
Another advantage of a fractional-N architecture and method according to the present invention is that subharmonic spurs or fractional spurs can be kept low.
Another advantage of a fractional-N architecture and method according to the present invention is that the spurious signal cancellation can occur dynamically.
Another advantage of a fractional-N architecture and method according to the present invention is that it avoids the need for compensation current trimming.
Another advantage of a fractional-N architecture and method according to the present invention is that it is robust to environmental changes.
To achieve the above objects in a whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described, a phase locked loop includes a first phase detector that receives an input signal and a first divided signal to output a first comparison signal, a second phase detector that receives the input signal and a second divided signal to output a second comparison signal, a loop filter that receives the first and second comparison signals and generates an output signal responsive to the comparison signals, a voltage-controlled oscillator that receives the output signal from the loop filter and generates a prescribed frequency signal, and a programmable modulus divider that receives the prescribed frequency signal and generates the first and second divided signals having a prescribed phase relationship.
To further achieve the above obje
Huh Hyungki
Koo Yi-do
Lee Jeongwoo
Lee Kang Yoon
Lee Kyeongho
Bocure Tesfaldet
Fleshner & Kim LLP
GCT Semiconductor Inc.
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