FPGA with time-multiplexed interconnect

Details FPGA with time-multiplexed interconnect FPGA with time-multiplexed interconnect

2007-09-11

2007-09-11

Cho, James (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S041000, C326S047000

Reexamination Certificate

active

11111229

ABSTRACT:
A programmable logic device (PLD) includes a plurality of configurable resources, a programmable interconnect having a plurality of signal lines for providing a number of dedicated signal paths between any of the configurable resources, and a subway routing system having a shared subway bus coupled to the signal lines of the programmable interconnect at a plurality of connection points by a plurality of corresponding subway ports. The subway routing system, which provides alternate routing resources for the programmable interconnect, may be used to route different signals between different configurable resources at different times.

REFERENCES:
patent: 5498975 (1996-03-01), Cliff et al.
patent: 5581199 (1996-12-01), Pierce et al.
patent: 5682107 (1997-10-01), Tavana et al.
patent: 6084429 (2000-07-01), Trimberger
patent: 6829756 (2004-12-01), Trimberger
patent: 7012448 (2006-03-01), Parkes

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