Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2000-08-29
2001-09-18
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S038000, C326S093000
Reexamination Certificate
active
06292021
ABSTRACT:
TECHNICAL FIELD
The present invention relates to programmable multifunctional digital logic array integrated circuits of the type known as field programmable gate arrays (FPGAs), and in particular to improvements in the structure of the configurable logic cells of such FPGAs, as well as of the direct cell-to-cell connections and of the interconnecting bus network of such FPGAs, designed to improve cell utilization and functionality for carrying out logic functions. The invention also relates to FPGAs that include user-accessible memory elements therein for integrating some memory storage capability for use by the FPGA devices' logic cells.
BACKGROUND ART
Digital logic can be implemented using any of several available integrated circuit architectures, including hardwired application-specific integrated circuits (ASICs), mask or fuse-programmed custom gate arrays (CGAs), programmable array logic (PALs), programmable logic arrays (PLAs) and other programmable logic devices (PLDS) that typically employ nonvolatile EPROM or EEPROM memory cell technology for configuration by the user, and field programmable gate arrays (FPGAs) which generally use SRAM configuration bits that are set during each power-up of the chip. Among these various architectures, those with user programmable, erasable and reprogrammable capability are usually preferred over those with fixed or only one-time programmable functionality. FPGAs are capable of implementing large highly complex logic functions, that need not be converted to two-level sum-of-products form to be programmed into these devices. The SRAM-controlled switches not only permit different functions to be loaded so as to very easily reconfigure a device, but also are optimized for high speed operation.
A wide variety of FPGAs are now available, which differ in the complexity of their component logic cells, as well as in the interconnect resources that are provided. FPGAs are disclosed, for example, in U.S. Pat. Nos. 4,706,216; 4,758,985; 5,019,736; 5,144,166; 5,185,706; 5,231,588; 5,258,688; 5,296,759; 5,343,406; 5,349,250; 5,352,940; 5,408,434; and many others.
A typical FPGA architecture is composed of a two-dimensional array or matrix of configurable logic cells that can be selectively linked together by a programmable interconnect structure made up of both direct connections between neighboring logic cells and a network of bus lines and connecting switches distributed between the rows and columns of cells in the matrix. Around the perimeter of the matrix, a set of input/output pads connect to the bus network, the perimeter logic cells or both, allowing signals to be transmitted into and out of the chip. Each individual logic cell is programmed to carry out a relatively simple logic function. Each logic cell typically includes input and output select logic (MUXes), combinatorial logic, one or more storage elements (flip-flop registers) for synchronous operation, and possibly one or more internal feedback lines for performing sequential logic. The combinatorial logic in the cells of some FPGAs is in the form of fixed-function logic gates, possibly with selectable input configurations. However, a preferred FPGA cell uses look-up table memory (configured SRAM) to provide a wider variety of logic functions. The memory cells of the look-up table store a set of data bits whose values correspond to the truth table for a particular function. A set of input signals presented on the memory's address lines causes the memory to provide a one-bit output that is the value stored at the address designated by those input signals. Hence, the look-up table memory implements a function determined by the stored truth values in the memory. The interconnect structure provides direct connections between each cell and its nearest neighbors in the same row or column of the matrix. U.S. Pat. No. 5,296,759 additionally provides connections in one direction to diagonally adjacent cells. In addition to the direct cell-to-cell connections, a set of “local” bus lines provide connections between the cells and a bussing network. Regularly spaced configurable switches, called repeater units, connect the short local bus segments to longer express busses. The repeaters are normally aligned in rows and columns, thereby partitioning the overall array into blocks of cells. One common arrangement organizes groups of 64 logic cells into 8×8 blocks, each having an associated set of local bus segments. Unlike the local bus segments, the express busses span more than one block of cells across the repeaters allowing signals to be routed between different blocks of cells. The express bus lines access the logic cells only through the local bus segments, reducing signal propagation delays on the express lines.
FPGA designers are continuing to make improvements in an attempt to increase the speed and functional flexibility of the devices. For example, it is a design goal to increase the functional capabilities of the individual logic cells, while at the same time keeping the cells small and simple, which is a principal characteristic of the FPGA architecture. A further area in need of improvement is the overall cell utilization of the circuit. In particular, due to a number of trade-offs and inefficiencies in the bussing network and cell-bus interface, FPGA cells are often used merely as “wire-cells” for routing signals between other cells, providing right angle turns, cross-over connections and signal fanout. Such signal routing is an inefficient use of logic cells. Ideally routing would be provided only by the direct connections and bussing network, while logic cells would be used only for logic. Also, because of the relative simplicity of the functions performed by individual cells, some designs provide cells dedicated to carrying out special functions, such as decoding and fast carry operations. Unfortunately, if the particular function is not needed, that cell is wasted. Cell design itself can contribute to the overall utilization of cells in an array. Preferably, the cells have mirror and rotational symmetry with respect to the functions available to its plural inputs and outputs, reducing the need for signal turning and simplifying the function layout of the array of cells. Finally, in most FPGAs, there is a need for user-accessible random access memory (RAM). Various manufacturers use different approaches to provide this needed on-chip memory. For example, Altera provides RAM on the outer edge of the array, while Actel provides alternating bands of logic cells and RAM. Xilinx allows the look-up table memory within the logic cells to be updated by the user during device operation so as to change the functions provided by those cells.
An object of the present invention is to provide an FPGA with increased logic-cell functionality, improved cell utilization, more efficient signal routing by the bussing network and direct cell-to-cell connections, and integrated user-accessible memory capability in the device.
DISCLOSURE OF THE INVENTION
The object is met by an FPGA matrix in which user-accessible memory structures (or dedicated logic), i.e. both the memory structures and the dedicated logic considered as “dedicated function elements”, is provided in the normally empty spaces at the corners of each block of logic cells at the intersection of rows and columns of repeater switch units. One type of memory structure could be random access memory, i.e., a RAM structure. Address and data lines of the RAM are connected to the bus lines, as are the write enable and output enable control ports of the RAM. The RAM may be either a single-port or dual-port SRAM. Pairs of adjacent columns of RAM may be addressed by the same set of bus lines. The memory structures could also be non-volatile memory structures.
The object is also met by an FPGA matrix in which repeater switch units connecting the local bus segments associated with a block of logic cells are spaced regularly after every N logic cells, thereby partitioning the cells into N×N blocks of cells, with the cells in each b
Furtek Frederick C.
Luking Robert B.
Mason Martin T.
Atmel Corporation
Le Don Phu
Protsik Mark
Schneck Thomas
Tokar Michael
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