FPGA repeatable interconnect structure with hierarchical interco

Details FPGA repeatable interconnect structure with hierarchical interco FPGA repeatable interconnect structure with hierarchical interco

1997-02-26

1999-06-22

Tokar, Michael

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 39, 326 40, H03K 19177

Patent

active

059146168

ABSTRACT:
The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. A combination of single-length lines connecting to adjacent tiles and intermediate-length lines connecting to tiles several tiles away creates an interconnect hierarchy which allows any logic block to be connected to any other logic block, yet also allows for fast paths to both adjacent tiles and tiles some distance away. Longer interconnect lines may be included as a third level of hierarchy to permit interconnection of widely separated tiles. In a preferred embodiment, from a given tile an intermediate-length line connects to the tile three tiles away, then continues and connects to the tile six tiles away. In this embodiment, the intermediate-length line does not connect to the intervening tiles one, two, four, and five tiles away.

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