FPGA lookup table with transmission gate structure for...

Details FPGA lookup table with transmission gate structure for... FPGA lookup table with transmission gate structure for...

2002-09-10

2003-12-23

Le, Don (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000

Reexamination Certificate

active

06667635

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to Field Programmable Gate Arrays (FPGAs). More particularly, the invention relates to a lookup table for an FPGA that is designed for reliable low-voltage operation.
BACKGROUND OF THE INVENTION
Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. Some FPGAs also include additional logic blocks with special purposes (e.g., DLLS, RAM, and so forth).
The CLBs, IOBs, interconnect, and other logic blocks are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect are configured. The configuration data can be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
A CLB typically includes at least two types of sub-circuits, with supporting logic. One sub-circuit type is the register element, which can be, for example, a flip-flop configurably programmable as a latch. The other common sub-circuit is a function generator, often a 4-input function generator that can provide any function of up to four input signals. The function generator is typically implemented as a lookup table (LUT), often a static RAM (SRAM).
For example, a 4-input LUT is typically implemented using a 16×1 SRAM. The SRAM is programmed (written to) during the configuration of the FPGA, using values included in the configuration bitstream. There are 16 possible combinations of the four input signals, so each of the 16 memory locations in the lookup table is programmed with the correct output value for the corresponding four input values. The four input values provide the four address bits for the 16×1 SRAM.
One FPGA, the Xilinx Virtex®-II FPGA, is described in detail in pages 33-75 of the “Virtex-II Platform FPGA Handbook”, published December, 2000, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference.
FIG. 1
is a simplified block diagram of a Virtex-II CLB.
CLB
100
includes four “slices” SLICE_
0
-
3
, each slice including the logic shown in
FIG. 1
for SLICE_
0
. (Other logic in the slice not relevant to the present application is omitted from
FIG. 1
, for clarity.) Each slice includes two LUTs
101
-
102
. Each LUT can be programmed to function as any of a 4-input lookup table, a 16-bit shift register, and 16 bits of random access memory (RAM) in any of several configurations. When the LUTs are configured to function as RAM, a write strobe generator circuit
105
is active, and controls the write functions of the RAM. Each LUT
101
-
102
has two output signals OUT
1
and OUT
2
. (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.) Both output signals OUT
1
-OUT
2
have the same value; the output value is provided in duplicate merely to speed up the output path for each output signal.
Multiplexer MUX
1
passes either the first output OUT
1
of function generator
101
or an independent input signal Reg_DI_
1
to 1-bit register
103
. Register
103
can be configured as either a flip-flop or a latch. The outputs of LUT
101
and register
103
are both optionally provided as outputs of the slice (labeled D
1
and Q
1
, respectively, in FIG.
1
). Thus, the LUT and register can be used independently of each other or can be coupled together so the register stores the LUT output signal.
The second LUT output, OUT
2
, is optionally used to control the carry logic within the half-slice. LUT output signal OUT
2
is coupled to the select terminal of carry multiplexer CM
1
, and selects one of the previous carry-out signal and a new input signal to place on the carry out terminal COUT.
The elements in the other half of the slice, including LUT
102
, multiplexer MUX
2
, carry multiplexer CM
2
, and 1-bit register
104
, are coupled together in a similar manner.
FIG. 2
shows the internal structure of the LUT included in the Virtex-II FPGA, i.e., LUTs
101
and
102
of FIG.
1
. Again, extraneous logic is omitted from the drawing, for clarity. For example, the configuration logic used to load initial values into RAM cells RB
201
-RB
216
is not shown. This logic and other omitted circuitry is well known in the art of FPGA design.
The Virtex-II LUT (
101
a
in
FIG. 2
) includes 16 memory cells RB
201
-RB
216
. These memory cells are used to store the 16 possible output values for the four input signals IN
1
-IN
4
. Memory cells RB
201
-RB
216
are accessed via several control and data signals. For example, signals CTRL/DATA
1
access each memory cell, and include configuration control signals, write control signals (such as write strobe signal WS shown in FIG.
1
), a direct data input signal (e.g., signals RAM_DI_
1
, RAM_DI_
2
in FIG.
1
), an initialization control signal, and so forth. Signals CTRL/DATA
2
pass serially through each memory cell, and include configuration input data, a serial line used when the LUT is configured as a serial register, and so forth.
Each memory cell RB
201
-RB
216
provides one output signal, of which one must be selected. The 16 output signals are reduced to four, first by eliminating half of the signals using input signal IN
1
, then by eliminating another half of the signals using input signal IN
2
. For example, the output of memory cell RB
201
passes through N-channel transistor
211
whenever signal IN
1
is high, while the output of memory cell RB
202
passes through N-channel transistor
212
whenever input signal IN
1
is low (i.e., the output of inverter INV
1
is high). The selected one of these two output signals passes through N-channel transistor
231
whenever signal IN
2
is high.
Similarly, the output of memory cell RB
203
passes through N-channel transistor
213
whenever signal IN
1
is high, while the output of memory cell RB
204
passes through N-channel transistor
214
whenever input signal IN
1
is low (i.e., the output of inverter INV
1
is high). The selected one of these two output signals passes through N-channel transistor
232
whenever signal IN
2
is low (i.e., the output of inverter INV
2
is high). Thus, the output of one of memory cells RB
201
-RB
204
is passed to node A, based on the values of signals IN
1
and IN
2
.
Similarly, the output of one of memory cells RB
205
-RB
208
is passed to node B, the output of one of memory cells RB
209
-RB
212
is passed to node C, and the output of one of memory cells RB
213
-RB
216
is passed to node D, also based on the values of signals IN
1
and IN
2
.
Coupled to each of nodes A-D is a pull-up (
241
-
244
, respectively) implemented as a P-channel transistor coupled between the node and power high VDD. The pull-up is controlled by power-on reset signal PORB. During a power-on or reset sequence signal PORB is low, forcing each of nodes A-D to a high value and ensuring thereby that the LUT output signals OUT
1
-OUT
2
are high after a power-on or reset sequence.
Node A then passes through a half-latch
245
to node E. Half-latch
245
includes an inverter
251
that buffers (and inverts) the signal on node A. However, a limitation of the circuit of
FIG. 2
now comes into play. This limitation is inherent in the properties of N-channel transistors, i.e., that a high voltage level passing through an N-channel transistor is reduced by one threshold voltage of the transistor. Therefore, to ensure that node A reaches a true “high” level (i.e., reaches power high VDD when the node is high), a second pull-up
261
is included, forming half-latch
245
. When node A is high, inverter
251
drives a low value, which

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