FPGA lookup table with high speed read decorder

Details FPGA lookup table with high speed read decorder FPGA lookup table with high speed read decorder

2002-11-15

2003-09-16

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S113000

Reexamination Certificate

active

06621296

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to programmable logic devices, and more particularly to lookup tables utilized in programmable logic devices.
BACKGROUND OF THE INVENTION
FIG. 1A
shows a basic Field Programmable Gate Array (FPGA)
100
, which is a type of Programmable Logic Device (PLD). FPGA
100
includes an array of configurable logic blocks (CLBs) CLB-
1
,
1
through CLB-
4
,
4
that are surrounded by input/output blocks (IOBs) IOB-
1
through IOB-
16
, and programmable interconnect resources that include vertical interconnect segments
120
and horizontal interconnect segments
121
extending between the rows and columns of CLBs and IOBs. Each CLB includes configurable combinational circuitry and optional output registers that are programmed to implement a portion of a user's logic function. The interconnect segments of the programmable interconnect resources are configured using various switches to generate signal paths between the CLBs that link the logic function portions. Each IOB is configured to selectively utilize an associated pin (not shown) of FPGA
100
either as a device input pin, a device output pin, or a bi-directional pin. Although greatly simplified, FPGA
100
is generally consistent with FPGAs that are produced, for example, by Xilinx, Inc. of San Jose, Calif.
FIGS. 1B through 1D
show examples of the various switches associated with the programmable interconnect resources of FPGA
100
.
FIG. 1B
shows an example of a six-way segment-to-segment switch
122
that selectively connects vertical wiring segments
120
(
1
) and
120
(
2
) and horizontal wiring segments
121
(
1
) and
121
(
2
) in accordance with configuration data stored in memory cells M
1
through M
6
. Alternatively, if horizontal and vertical wiring segments
120
and
121
do not break at an intersection, a single transistor makes the connection.
FIG. 1C
shows an example of a segment-to-CLB/IOB input switch
123
that selectively connects an input wire
110
(
1
) of a CLB or IOB to one or more interconnect wiring segments in accordance with configuration data stored in memory cells M
7
and M
8
.
FIG. 1D
shows an example of a CLB/IOB-to-segment output switch
124
that selectively connects an output wire
115
(
1
) of a CLB or IOB to one or more interconnect wiring segments in accordance with configuration data stored in memory cells M
9
through M
11
.
Since the first FPGA was invented in 1984, variations on the basic FPGA circuitry have been devised that allow FPGAs to implement specialized functions more efficiently. For example, special interconnection lines have been added to allow adjacent CLBs to be connected at high speed and without taking up general interconnection lines. In addition, hardware has been placed between adjacent CLBS that allows fast carry signal transmissions when an FPGA is configured to implement an arithmetic function or certain wide logic functions. Finally, the circuitry associated with the CLBs has undergone several changes that allow each CLB to implement specialized functions more efficiently. Such CLB modifications are particularly relevant to the present invention.
FIG. 2
shows a CLB used in the Virtex™ series of FPGAs produced by Xilinx, Inc. (Virtex is a trademark of Xilinx, Inc., assignee of the present patent application.) The CLB includes two slices SLICE-
0
and SLICE-
1
. Each slice includes a pair of four-input lookup tables (LUTs) LUT F and LUT G, a pair of registers FF-X and FF-Y, and additional arithmetic carry and control (CARRY & CNTRL) logic. The output signal from each LUT is programmably controlled such that it is either transmitted directly to the surrounding interconnect resources (not shown), or applied to the D input of an associated register. Additional information regarding registers FF-X and FF-Y and the carry and control circuitry of the CLB can be found in the “Virtex™ 2.5 V Field Programmable Gate Arrays Advance Product Specification”, which was made available Mar. 13, 1999 on the World Wide Web at http://www.Xilinx.com/partinfo/virtex.pdf, and is incorporated herein by reference. A paper copy of this Mar. 13, 1999 document can be obtained from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124.
FIG. 3A
shows a lookup table (LUT)
300
that is used to implement LUT-G in the Virtex CLB shown in FIG.
2
. LUT
300
includes a predecoder
310
, a latch circuit
320
, a write decoder
330
, a memory block
340
and a read decoder
350
. Input terminals IN
1
through IN
4
receive input signals from interconnect lines (see
FIGS. 1A
,
1
C) of a host FPGA. These input signals are transmitted to predecoder
310
, which generates an eight-bit address signal on read address lines R
1
trough R
8
in response to the input signals. Read address lines R
1
through R
8
transmit the address signal to read decoder
350
. In addition, the read address lines R
1
through R
8
of one LUT (LUT-G in
FIG. 2
) are connected to latch circuit
320
. Latch circuit
320
temporarily stores the eight bits of the address signal transmitted on read address lines R
1
through R
8
, and applies the eight bits as a write address signal to write address lines W
1
through W
8
. This write address signal is applied to write decoder
330
, and is also transmitted to the write decoder of the second LUT of the Virtex™ CLB (i.e., LUT-F; see FIG.
2
). In other devices, such as those in Xilinx's XC4000™ series of FPGAs, each LUT of a CLB has independent write address lines.
Memory block
340
includes sixteen memory circuits PMC-
1
through PMC-
16
. As discussed below, each memory circuit PMC-
1
through PMC-
16
is capable of storing one data bit. Data bits are stored during configuration, and read during a read-back operation. During the configuration mode, data bits are transmitted to memory circuits PMC-
1
through PMC-
16
using address and data signals transmitted from a configuration bus (CONFIG BUS). During a memory write operation, data bits transmitted through a data-in DIN terminal are passed to memory cell input terminals QIN of selected memory circuits PMC-
1
through PMC-
16
by write decoder
330
. Each data bit is passed to a selected QIN terminal based on the write address signal transmitted to write decoder
330
on write address lines W
1
through W
8
. During subsequent memory read operations, data bits are transmitted from memory circuit output terminals QO of selected memory circuits to a LUT output terminal OUT by read decoder
350
in response to the read address signals transmitted on read address lines R
1
through R
8
.
In addition to the configuration mode and memory read/write operations, LUT
300
can implement a shift register. During shift register operations, data bits are transmitted directly from the DIN terminal to the shift-in terminal SIN of memory circuit PMC-
1
, and then transmitted sequentially from the QO terminals of each memory circuit to the SIN terminals of a subsequent memory circuit. This shift register structure is further described by Bauer in U.S. Pat. No. 5,889,413 [Docket X-275], which is incorporated herein by reference.
FIGS. 3B through 3F
show additional details of LUT
300
.
FIG. 3B
shows relevant portions of predecoder
310
. Predecoder
310
receives input signals on LUT input terminals IN
1
through IN
4
. These input signals are inverted by first inverters
313
, and are transmitted in non-inverted and inverted forms to NAND gates
315
. NAND gates
315
generate output signals based on the logical NAND of selected pairs of the non-inverted or inverted input signals. These output signals are transmitted from NAND gates
315
to second inverters
317
which generate the eight read address signals R
1
through R
8
.
FIG. 3C
shows write decoder
330
of CLB
300
. A data input signal DIN is passed to the QIN terminal of a memory cell PMC-
1
through PMC-
16
as selected by write address signals W
1
through W
8
.
FIG. 3D
shows read decoder
350
of LUT
300
. Decoder
350
selects an output signal QO from one of memory cells PMC-
1
through PMC-

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