FPGA logic element with variable-length shift register...

Details FPGA logic element with variable-length shift register... FPGA logic element with variable-length shift register...

2001-04-27

2002-05-14

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S041000

Reexamination Certificate

active

06388466

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to Programmable Logic Devices (PLDS) such as Field Programmable Gate Arrays (FPGAs). More particularly, the invention relates to an FPGA logic element having variable-length shift register capability.
BACKGROUND OF THE INVENTION
Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that may be programmed by a user to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect lines are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect are configured. The configuration data may be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
CLBs typically include both logic elements and storage elements (e.g., flip-flops). Each logic element implements a logic function of the n inputs to the logic element according to how the logic element has been configured. Logic functions may use all n inputs to the logic element or may use only a subset thereof. A few of the possible logic functions that a logic element can be configured to implement are: AND, OR, XOR, NAND, NOR, XNOR and mixed combinations of these functions.
One known implementation of the logic element includes a configurable lookup table that is internal to the logic element. This lookup table includes 2
n
individual memory cells, where n is the number of input signals the lookup table can handle. At configuration, in this architecture a bitstream programs the individual memory cells of the lookup table with a desired function by writing the truth table of the desired function to the individual memory cells.
One memory cell architecture appropriate for use in the lookup tables is shown in FIG.
1
and described by Hsieh in U.S. Pat. No. 4,821,233. A memory cell of this architecture is programmed by applying the value to be written to the memory cell on the data input line DATA and strobing the corresponding address line ADDR. Further, although memory cell M is implemented using five transistors, other known configurations, e.g., six transistor static memory cells, also are appropriate choices for implementing the memory cells of the lookup table. As shown in
FIG. 1
, inverter
726
may be included to increase the drive of memory cell
700
, and avoid affecting the value stored in memory cell
700
unintentionally via charge sharing with the read decoder.
After configuration, to use a lookup table, the input lines of the configured logic element act as address lines that select a corresponding memory cell in the lookup table. For example, a logic element configured to implement a two-input NAND gate provides the corresponding value {1,1,1,0} contained in the one of the four memory cells corresponding to the current input pair {00, 01, 10, 11}, respectively. The selection of the memory cell to be read is performed by a decoding multiplexer, which selects a memory cell from the lookup table on the basis of the logic levels on the input lines.
FIG. 2
shows a block diagram of an exemplary 4-input lookup table including 16 memory cells
700
1
through
700
16
and a decoding multiplexer
200
. Multiplexer
200
propagates a value stored in exactly one of the memory cells
700
1
-
700
16
of the lookup table to an output X of the lookup table as selected by the four input signals F
0
-F
3
. (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.)
FIG. 3
is a schematic diagram of a known 2-input lookup table. This lookup table is implemented using four memory cells
700
1
-
700
44
and a two-input decoding multiplexer
200
with two input signals, F
0
and F
1
. The two-input decoding multiplexer
200
is shown in detail as being implemented by a hierarchy of pass transistors, which propagate the value stored in the selected memory cell to the output X of the logic element. In
FIG. 3
, the memory cells can be implemented, for example, as shown in FIG.
1
.
The above architecture was later augmented to enhance the functionality of the lookup tables. Freeman et al., in U.S. Pat. No. 5,343,406, describe how additional circuitry can enable lookup tables to behave as random access memories (RAMs) that can be both read and written after configuration of the logic device. When the option of allowing the user to write data to memory cells is available, there also must be provision for entering the user's data into these memory cells and reading from the memory cells. This capability is provided by including two means for accessing each dual function memory cell, one of which is used to supply the configuration bitstream from off the chip, and the other of which is used during operation to store values from signals that are routed from the interconnect lines of the FPGA.
FIG. 4
shows the memory cell architecture described by Freeman et al. in U.S. Pat. No. 5,343,406, which allows memory cell
750
to be programmed both during and after configuration. During configuration, memory cell
750
is programmed using the same process for programming the memory cell of FIG.
1
. After configuration, memory cell
750
is programmed differently. A value to be written to memory cell
750
is applied through the interconnect structure of the FPGA to the second data line
705
, and then the corresponding write-strobe line WS for the memory cell is pulsed. This pulse latches the value on line
705
into memory cell
750
. Like the lookup table of
FIG. 2
, which uses a series of memory cells from
FIG. 1
, a series of memory cells from
FIG. 4
are combinable into a lookup table. The resulting lookup table can also be optionally used as a RAM after the conclusion of the configuration process.
FIG. 5
is a block diagram showing a 4-input lookup table with synchronous write capability. The lookup table of
FIG. 5
includes a write strobe generator
504
that receives a clock signal CK and a write enable signal WE, and creates a single write strobe signal WS for the lookup table. To write a value to a desired memory cell, for example memory cell
750
5
, the value is applied on line D
in
and the address of the desired memory cell
750
5
is applied to the input lines F
0
-F
3
of demultiplexer
500
. The value is then latched into the desired memory cell
750
5
by pulsing the write strobe signal WS. Conversely, to read a value stored in a different desired memory cell
750
3
, the address of the memory cell
750
3
is applied to the input lines F
0
-F
3
of decoding multiplexer
200
(without pulsing the write strobe), as was described with reference to
FIGS. 2 and 3
.
FIG. 6
is a schematic illustration of a 2-input lookup table with synchronous write capability. The lookup table of
FIG. 6
includes four memory cells
750
1
through
750
4
. Details of demultiplexer
500
and multiplexer
200
are shown in FIG.
6
.
One or more 4-input lookup tables, such as those illustrated in
FIGS. 2 and 5
, are typically used to implement combinatorial function generators in a CLB. Because a 4-input lookup table is only capable of storing 16 bits of data, CLE architectures have been designed that allow the combination of two lookup tables to form larger structures. For example, some CLBs include a third function generator selecting between the outputs of two 4-input lookup tables, which enables the CLB to implement any 5-input function. One such CLB, implemented in the Xilinx XC4000-Series FPGAs, is described in pages 4-9 through 4-21 of the Xilinx 1998 Data Book entitled “The Programmable Logic Data Book 1998”, published in 1998 and available from Xilinx, Inc., 2100

Affiliated with

Also associated with

Rating

FPGA logic element with variable-length shift register... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with FPGA logic element with variable-length shift register..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and FPGA logic element with variable-length shift register... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2860664