FPGA having predictable open-drain drive mode

Details FPGA having predictable open-drain drive mode FPGA having predictable open-drain drive mode

1997-07-24

2000-02-22

Tokar, Michael

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 39, 326 44, 326 37, H03K 19177, H01L 2500, G06F 738

Patent

active

060284471

ABSTRACT:
A field-programmable gate array (FPGA) having at least one programmable cell (e.g., an input/output (I/O) cell) having an output node circuit (e.g., a pad circuit) in which the output data signal and the tri-state signal are applied to a multiplexer that drives the tri-state port of an output buffer in the output node circuit. This configuration enables the output node circuit to be configured for open drain drive mode operations in a fast, predictable manner that does not need to rely on the FPGA's general routing resources.

REFERENCES:
patent: 5144166 (1992-09-01), Camarota et al.
patent: 5233539 (1993-08-01), Agrawal et al.
patent: 5311080 (1994-05-01), Britton et .
patent: 5329180 (1994-07-01), Popli et al.
patent: 5329460 (1994-07-01), Agrawal et al.
patent: 5671432 (1997-09-01), Bertolet et al.

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