Electronic digital logic circuitry – Multifunctional or programmable – Array
Patent
1997-03-14
1999-03-30
Tokar, Michael
Electronic digital logic circuitry
Multifunctional or programmable
Array
326 41, H03K 19177
Patent
active
058894110
ABSTRACT:
An aspect of the invention provides an FPGA interconnect and logic block structure preferably included in an array of identical tiles. By allowing the complement of a carry multiplexer input signal to be another carry multiplexer input signal, an optional inverter can be formed and a carry chain running from one tile to the next can be used for generating wide XOR functions as well as other combinational functions and arithmetic functions.
REFERENCES:
patent: Re34363 (1993-08-01), Freeman
patent: 4124899 (1978-11-01), Birkner et al.
patent: 4642487 (1987-02-01), Carter
patent: 4706216 (1987-11-01), Carter
patent: 4750155 (1988-06-01), Hsieh
patent: 4758745 (1988-07-01), Elgamal et al.
patent: 4821233 (1989-04-01), Hsieh
patent: 4870302 (1989-09-01), Freeman
patent: 5001368 (1991-03-01), Cliff et al.
patent: 5073729 (1991-12-01), Greene et al.
patent: 5079451 (1992-01-01), Gudger et al.
patent: 5122685 (1992-06-01), Chan et al.
patent: 5144166 (1992-09-01), Camarota et al.
patent: 5148390 (1992-09-01), Hsieh
patent: 5157618 (1992-10-01), Ravindra et al.
patent: 5185706 (1993-02-01), Agrawal et al.
patent: 5198705 (1993-03-01), Galbraith et al.
patent: 5208491 (1993-05-01), Ebeling et al.
patent: 5231588 (1993-07-01), Agrawal et al.
patent: 5241224 (1993-08-01), Pedersen et al.
patent: 5243238 (1993-09-01), Kean
patent: 5245227 (1993-09-01), Furtek et al.
patent: 5258668 (1993-11-01), Cliff
patent: 5260610 (1993-11-01), Pedersen et al.
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5260881 (1993-11-01), Agrawal et al.
patent: 5267187 (1993-11-01), Hsieh et al.
patent: 5280202 (1994-01-01), Chan
patent: 5313119 (1994-05-01), Cooke et al.
patent: 5317209 (1994-05-01), Garverick et al.
patent: 5319255 (1994-06-01), Garverick et al.
patent: 5323069 (1994-06-01), Smith, Jr.
patent: 5333279 (1994-07-01), Dunning
patent: 5343406 (1994-08-01), Freeman et al.
patent: 5347519 (1994-09-01), Cooke et al.
patent: 5349250 (1994-09-01), New
patent: 5357153 (1994-10-01), Chiang et al.
patent: 5359242 (1994-10-01), Veenstra
patent: 5365125 (1994-11-01), Goetting et al.
patent: 5455525 (1995-10-01), Ho et al.
patent: 5457410 (1995-10-01), Ting
patent: 5469003 (1995-11-01), Kean
patent: 5481206 (1996-01-01), New et al.
patent: 5500609 (1996-03-01), Kean
patent: 5504440 (1996-04-01), Sasaki
patent: 5537057 (1996-07-01), Leong et al.
patent: 5543732 (1996-08-01), McClintock et al.
patent: 5546018 (1996-08-01), New et al.
patent: 5546596 (1996-08-01), Geist
patent: 5581199 (1996-12-01), Pierce et al.
patent: 5583450 (1996-12-01), Trimberger et al.
patent: 5629886 (1997-05-01), New
patent: 5635851 (1997-06-01), Tavana
patent: 5645546 (1997-07-01), Bertolet et al.
patent: 5682107 (1997-10-01), Tavana et al.
patent: 5724276 (1998-03-01), Rose et al.
patent: 5740069 (1998-04-01), Agrawal et al.
patent: 5760604 (1998-06-01), Pierce et al.
"The Programmable Logic Data Book", 1996, available from Xilinx Inc., 2100 Logic Drive, San Jose, California, 95124, pp. 4-1 to 4-49.
Neil H. W. Weste and Klamran Eshraghian, "Principles of CMOS VLSI: A Systems Approach", by AT&T Bell Laboratories, Inc, published by Addison-Wesley Publishing Company, copyright 1985, pp. 56.
"The Programmable Gate Array Data Book", 1989, available from Xilinx Inc., 2100 Logic Drive, San Jose, California, 95124, pp. 6-30 through 6-44.
"The Programmable Logic Data Book", 1993, available from Xilinx Inc., 2100 Logic Drive, San Jose, California, 95124 pp. 1-1 through 1-7; 2-1 through 2-42; 2-97 through 2-130; and 2-177 through 2-204.
Luis Morales, "Boundary Scan in XC4000 Devices", XAPP 017.001, Oct. 1992, pp. 2-108 and 2-180.
Xilinx, Inc., "The Programmable Logic Data Book"1996, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, pp. 4-11 to 4-23 and 4-32 to 4-37.
Lucent Technologies Microelectronics Group, ORCA, "Field-Programmable Gate Arrays Data Book," Oct. 1996, pp. 2-9 to 2-20.
Altera Corporation, "Flex 10K Embedded Programmable Logic Family Data Sheet" from the Altera Digital Library, 1996, available from Altera Corporation, 2610 Orchard Parkway, San Jose, CA 95134-2020, pp. 31-53.
Duong Qui Van
Tokar Michael
Xilinx , Inc.
Young Edel M.
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