Electronic digital logic circuitry – Multifunctional or programmable – Array
Patent
1998-08-04
2000-05-30
Tokar, Michael
Electronic digital logic circuitry
Multifunctional or programmable
Array
326 39, 326 38, 714725, G06F 738
Patent
active
060694890
ABSTRACT:
An FPGA configuration memory is divided into columnar frames each having a unique address. Configuration data is loaded into a configuration register, which transfers configuration data frame by frame in parallel. In a preferred embodiment, an input register, a shadow input register and a multiplexer array permit efficient configuration data transfer using a larger number of input bits than conventional FPGAs. A flexible external interface enables connection with bus sizes varying from a predetermined maximum width down to a selected fraction thereof. Configuration data transfer is made more efficient by using shadow registers to drive such data into memory cells on a frame-by-frame basis with a minimum of delay, and by employing a multiplexer array to exploit a wider configuration data transfer bus. The speed of configuration readback is made substantially equal to the rate of configuration data input by employing configuration register logic that supports bidirectional data transfer. Using the invention, a bit stream designed for an old device can be used for a new device having additional configuration memory cells.
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Iwanczuk Roman
Schultz David P.
Young Steven P.
Cartier Lois D.
Hoffman, Esq. Eric
Tokar Michael
Tran Anh
Xilinx , Inc.
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