FPGA customizable to accept selected macros

Details FPGA customizable to accept selected macros FPGA customizable to accept selected macros

2001-08-07

2002-04-30

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C326S041000, C326S047000, C326S008000, C326S101000, C365S185040, C713S193000, C713S152000

Reexamination Certificate

active

06381732

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to programmable devices such as field programmable gate arrays (FPGAs). More specifically, the present invention relates to methods for programming and enabling licensed macros in an FPGA.
BACKGROUND OF THE INVENTION
Due to advancing semiconductor processing technology, integrated circuits have greatly increased in functionality and complexity. For example, programmable devices such as field programmable gate arrays (FPGAs) and programmable logic devices (PLDs), can incorporate ever-increasing numbers of functional blocks and more flexible interconnect structures to provide greater functionality and flexibility.
FIG. 1
is a simplified schematic diagram of a conventional FPGA
110
. FPGA
110
includes user logic circuits such as input/output blocks (IOBs), configurable logic blocks (CLBs), and programmable interconnect
130
, which contains programmable switch matrices (PSMs). Each IOB and CLB can be configured through configuration port
120
to perform a variety of functions. Programmable interconnect
130
can be configured to provide electrical connections between the various CLBs and IOBs by configuring the PSMs and other programmable interconnection points (PIPS, not shown) through configuration port
120
. Typically, the IOBs can be configured to drive output signals or to receive input signals from various pins (not shown) of FPGA
110
.
FPGA
110
also includes dedicated internal logic. Dedicated internal logic performs specific functions and can only be minimally configured by a user. For example, configuration port
120
is one example of dedicated internal logic. Other examples may include dedicated clock nets (not shown), power distribution grids (not shown), and boundary scan logic (i.e. IEEE Boundary Scan Standard 1149.1, not shown).
FPGA
110
is illustrated with 16 CLBs, 16 IOBs, and 9 PSMs for clarity only. Actual FPGAs may contain thousands of CLBs, thousands of IOBs, and thousands of PSMs. The ratio of the number of CLBs, IOBs, and PSMs can also vary.
FPGA
110
also includes dedicated configuration logic circuits to program the user logic circuits. Specifically, each CLB, IOB, PSM, and PIP contains a configuration memory (not shown) which must be configured before each CLB, IOB, PSM, or PIP can perform a specified function. Some FPGAs may also include pre-configured logic circuits that are configured by the manufacturer to perform specific functions.
For example, some FPGAs are pre-configured to include a PCI bus interface. Typically the configuration memories within an FPGA use static random access memory (SRAM) cells. The configuration memories of FPGA
110
are connected by a configuration structure (not shown) to configuration port
120
through a configuration access port (CAP)
125
. A configuration port (a set of pins used during the configuration process) provides an interface for external configuration devices to program the FPGA. The configuration memories are typically arranged in rows and columns. The columns are loaded from a frame register which is in turn sequentially loaded from one or more sequential bitstreams. (The frame register is part of the configuration structure referenced above.) In FPGA
110
, configuration access port
125
is essentially a bus that couples configuration port
120
to the configuration structure of FPGA
110
.
FIG. 2
illustrates a conventional method used to configure FPGA
110
. Specifically, FPGA
110
is coupled to a configuration device
230
such as a serial programmable read only memory (SPROM), an electrically programmable read only memory (EPROM), or a microprocessor. Configuration port
120
receives configuration data, usually in the form of a configuration bitstream, from configuration device
230
. Typically, configuration port
120
contains a set of mode pins, a clock pin and a configuration data input pin. Configuration data from configuration device
230
is transferred serially to FPGA
110
through the configuration data input pin. In some embodiments of FPGA
110
, configuration port
120
comprises a set of configuration data input pins to increase the data transfer rate between configuration device
230
and FPGA
110
by transferring data in parallel. However, due to the limited number of dedicated function pins available on an FPGA, configuration port
120
usually has no more than eight configuration data input pins. Further, some FPGAs allow configuration through a boundary scan chain. Specific examples for configuring various FPGAs can be found on pages 4-46 to 4-59 of “The Programmable Logic Data Book”, published in January, 1998 by Xilinx, Inc., and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference. Additional methods to program FPGAs are described by Lawman in U.S. Pat. No. 6,028,445, which is hereby incorporated by reference.
As explained above, actual FPGAs can have thousands of CLBs, IOBs, PSMs, and PIPs; therefore, the design and development of FPGA software is very time-consuming and expensive. Consequently, many vendors provide macros for various functions that can be incorporated by an end user of the FPGA into the user's own design file. For example, Xilinx, Inc. provides a PCI interface macro, which can be incorporated by an end user into the user's design file. The user benefits from the macro because the user does not need to spend the time or resources to develop the macro. Further, since the vendor profits from selling the same macro to many users, the vendor can spend the time and resources to design optimized macros. For example, the vendor strives to provide macros having high performance, flexibility, and low gate count. However, the macro vendors are reluctant to give out copies of the design macros without a way of insuring that the design macros are used only by licensed users. Hence, there is a need for a method or structure to insure third party macros are used only by licensed end users.
SUMMARY OF THE INVENTION
The present invention uses on-chip keys, i.e., keys programmed into the chip, to unlock locked macros before the macros will function. Thus, macro vendors can freely distribute locked macros as long as the key to the macro is secure. A macro vendor locks a macro using a lock to create a locked macro. A corresponding key is placed within the FPGA in a write-only memory or a write and read once memory. (A read-once memory is a memory that can be read back only once, e.g., for manufacturing test purposes.) During configuration of the FPGA, a decoder detects the locked macro and uses the key to unlock the locked macro.
An FPGA in accordance with one embodiment of the present invention comprises a configuration port, a decoder coupled to the configuration port, a key table coupled to the decoder and the configuration port, and a configuration access port coupled to the decoder. In one embodiment the key table is a memory that is write-only from outside the FPGA. However, in another embodiment, the key table has visible header sections and invisible key sections. The visible header sections can be written to and read from outside the FPGA via the configuration port. The invisible key sections are write-only from outside the FPGA.
When an end user wishes to incorporate a locked macro from a macro vendor, the macro vendor pre-programs a key into the key table of the FPGA. The end user creates a design file incorporating the locked macro. The design file is then converted into configuration data for the FPGA. The configuration data is sent into the configuration port of the FPGA. The on-chip decoder processes the configuration data and detects the locked macro. When the locked macro is detected, the decoder uses the key in the key table to unlock the locked macro. If the key table does not contain a key able to unlock the locked macro, configuration of the FPGA fails. If additional locked macros are desired, the macro vendor can pre-program additional keys into the FPGA. Thus, a macro vendor can freely distribute the locked macr

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