FPGA control structure for self-reconfiguration

Details FPGA control structure for self-reconfiguration FPGA control structure for self-reconfiguration

1999-01-26

2001-07-10

Butler, Dennis M. (Department: 2182)

Electrical computers and digital processing systems: support

Digital data processing system initialization or configuration

C713S100000

Reexamination Certificate

active

06260139

ABSTRACT:

FIELD OF THE INVENTION
The present invention is related generally to the self-reconfiguration of programmable devices, and more specifically to the self-reconfiguration of Field Programmable Gate Arrays (FPGAs).
BACKGROUND OF THE INVENTION
Programmable logic devices such as FPGAs have wide applicability due to their flexibility and reprogrammability. An FPGA typically includes an array of configurable logic blocks (CLBs) programmably interconnected to one another across a configurable routing structure to implement a user's desired logic functions and circuit design. FPGAs also include a number of configuration memory cells coupled to the CLBs to specify the function to be performed by each CLB, and a number of configuration memory cells coupled to the configurable routing structure to specify the connectivity between CLBs. FPGAs may also include data storage cells accessible by a user during device operation.
FPGAs are most commonly used within systems including a microprocessor or similar control device and a memory unit. Referring to
FIG. 1
, an available FPGA
120
receives a configuration bitstream from memory device
100
upon receipt of a PROGRAM signal from microprocessor
110
, causing the FPGA to erase its now-unwanted configuration data and prepare to receive new configuration data from memory
100
. Thus, while reconfiguring an FPGA within a controlled system to perform different logic functions at different times is known in the art, conventional reconfiguration techniques require fairly sophisticated and expensive control devices, such as microprocessor
110
, to instigate reconfiguration as needed for a particular system. There remains, therefore, a need in the art for a system capable of reconfiguring an FPGA without a sophisticated control device.
SUMMARY OF THE INVENTION
To address the shortcomings of the available art, the present invention provides a system, including a reprogrammable device, which initiates its own reconfiguration by driving an output signal onto the device's own configuration-initiating input terminal. Built-in delays and sequences in a preferred FPGA architecture permit reliable operation of the inventive system, since the received reconfiguration signal triggers a configuration sequence that, in turn, stops the output signal from continuing to drive the input terminal. The FPGA preferably initiates its own reconfiguration upon detecting that a new configuration (i.e., new configuration data for all or part of the FPGA) has been designated by a simple external control device. The FPGA then downloads the configuration from an external memory device. For example, the FPGA may detect the actuation of a binary or rotary switch. In another embodiment, the FPGA detects when a CMOS latch or a register points to a new address in the external memory device in which the configuration data is stored.
It is therefore a first advantage of the present invention to provide a self-reprogrammable system, the system including a monitoring circuit for detecting a monitored characteristic of an external signal, the monitoring circuit including means for generating a reconfiguration request signal in response to detection of a change in the monitored characteristic of the external signal, the system having an input terminal and an output terminal in electrical communication with the input terminal, the system being responsive to the reconfiguration request signal such that the system drives a signal on the output terminal into a first state and enters a reconfiguration mode in response to detection of the first state on the input terminal.
Another advantage of the present invention is the provision of a method of self-reconfiguration of a programmable device, the method including the steps of monitoring an external signal, determining whether there is a difference between a detected characteristic of the external signal at a first and second time, driving a signal on an output terminal of the programmable device into a first state in response to a determination that there is a difference between the detected characteristic at the first and the second time, detecting the first state of a signal on the output terminal at an input terminal of the programmable device, and causing the programmable device to enter a reconfiguration mode in response to detection of the first state.
A further advantage of the present invention is the provision of a system for causing self-reconfiguration in a programmable device, the system including means for monitoring an external signal, means for determining whether there is a difference between a detected characteristic of the external signal at a first and a second time, means for driving a signal on an output terminal of the programmable device into a first state in response to a determination that there is a difference between the detected characteristic at the first and the second time, means for detecting the first state of the signal on the output terminal at an input terminal of the programmable device, and means for causing the programmable device to enter a reconfiguration mode in response to detection of the first state.


REFERENCES:
patent: 5336950 (1994-08-01), Popli et al.
patent: 5784636 (1998-07-01), Rupp
patent: 5995744 (1999-11-01), Guccione
patent: 6038400 (2000-03-01), Bell et al.
patent: 6157210 (2000-12-01), Zaveri et al.
Peter H. Alfke, “An FPGA Can Control Its Own Reconfiguration”, XCELL, The Quarterly Journal for Xilinix Programmable Logic Users, Issue 27, published Feb. 13, 1998.

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