FPGA configuration circuit including bus-based CRC register

Details FPGA configuration circuit including bus-based CRC register FPGA configuration circuit including bus-based CRC register

1999-08-13

2001-02-20

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S041000, C326S040000, C326S039000, C326S038000

Reexamination Certificate

active

06191614

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to field programmable gate arrays (FPGAs). The invention particularly relates to a structure and method for configuring static random access memory (SRAM)-based FPGAs.
BACKGROUND OF THE INVENTION
The first FPGA with programmable logic cells and programmable routing was described by Freeman in U.S. Pat. No. 4,870,302, reissued as Re. 34,363, which is incorporated herein by reference. An FPGA includes configurable logic blocks and configurable routing, which are programmed by configuration memory cells. The configuration memory cells are typically arranged in an array and are loaded with a bit stream of configuration data. The configuration data is selected to cause the FPGA to perform a desired function.
FIG. 1A
shows a conventional array of configuration memory cells (i.e., a configuration memory array) such as that used by Xilinx, Inc., assignee of the present invention. The configuration memory array of
FIG. 1A
is a 16-bit by 16-bit array, which includes 256 configuration memory cells. In general, each of the configuration memory cells is identified by a reference character Mx,y, where x and y correspond to the row and column of the configuration memory cell. A typical array of configuration memory cells in a commercial device has on the order of 20,000 to one million memory cells. Therefore, the array of
FIG. 1A
is much smaller than is typically used in a commercial embodiment, but nevertheless shows the structure of prior art configuration memories.
To load data into the configuration memory array shown in
FIG. 1A
, the bit stream of configuration data is shifted through a data shift register DSR under control of a clocking mechanism until a frame of data (16 bits wide in this example) has been shifted into bit positions DS
0
through DS
15
of the data shift register DSR. This frame of data is then shifted in parallel on data lines D
0
through D
15
into a column of configuration memory cells addressed by address shift register ASR. The column is addressed by shifting a token high bit through the address shift register ASR from bit AS
0
to bit AS
15
, one shift per frame. Each time a frame of configuration data is loaded through data shift register DSR, it is shifted in parallel to the column of memory cells selected by the token high bit. When the token high bit shifts out to the right, it activates a DONE circuit, which indicates that configuration is complete and causes the FPGA to become operational.
FIG. 1B
is a simplified circuit diagram showing memory cell M
0
,
0
. Memory cell M
0
,
0
includes a latch formed by inverters I
1
and I
2
that stores a bit value transmitted through a pass transistor T
1
. During configuration, when the token high bit is shifted into address shift register bit AS
0
(FIG.
1
A), the resulting high signal on line A
0
is applied to the gate of pass transistor T
1
, thereby allowing the configuration bit stored in data shift register bit position DS
0
to enter the latch via data line D
0
. The value stored in memory cell M
0
,
0
is then applied via output line Q and/or Q-bar (QB) to control a corresponding configurable logic block or configurable routing resource.
While the configuration circuitry described above is adequate for configuring the conventional configuration memory array shown in
FIG. 1A
, it is inadequate for performing more advanced operations. For example, the configuration circuitry does not support partial reconfiguration (i.e., changing only some of the configuration data without addressing all of the configuration memory cells) because there is no mechanism for addressing individual frames.
SUMMARY OF THE INVENTION
The present invention provides a novel configuration circuit and method for configuring a programmable logic device (PLD) that facilitates advanced configuration operations (such as partial reconfiguration) while minimizing the number of device pins needed to control these operations.
The present invention is utilized in a PLD that includes configurable logic blocks (CLBs) connected by configurable interconnect resources, and a configuration circuit that includes memory cells coupled to the configurable logic blocks and the configurable interconnect resources. The PLD also includes one or more external communication circuits for transmitting a configuration bit stream between external devices and the memory cells. Configuration data in the bit stream is transmitted to the memory cells of the configuration memory circuit during a configuration operation. During subsequent normal operation of the PLD, the configuration data stored in the memory cells determines the logic function performed by the CLBs.
In accordance with an aspect of the present invention, the configuration memory circuit includes an internal, bi-directional bus, a bus interface circuit connected between the bus and one or more external communication circuits, and a plurality of configuration registers connected between the bus and the configuration memory array. During configuration operations, the bus interface circuit decodes a header word from the configuration bit stream, parses the header word to identify an address field, and enables a selected configuration register to receive a subsequent (second) word or words from the bit stream when the address field matches an address assigned to the selected configuration register. The second word transmitted to the selected configuration register may include, for example, a command word for causing the selected configuration register to perform a predetermined operation, an address identifying a portion of the configuration memory array for reconfiguration, or data to be written to the configuration memory array. Because address and command information, as well as configuration data, is transmitted into the PLD via the bit stream, the number of device pins required to provide a wide variety of advanced configuration operations is minimized.
In accordance with another aspect of the present invention, the bus interface circuit includes a multiplexer (switch) for passing a configuration bit stream between a selected external communication circuit and the configuration memory array. For example, configuration data is selectively written to or read from the configuration memory array through a JTAG circuit, or through bi-directional pins of the FPGA. Access to the configuration memory is possible through the JTAG circuit while a user's logic function is being executed by the CLBs and IOBs of the FPGA. Alternatively, access through the bi-directional pins is possible if these pins are not needed to implement the user's logic function. Therefore, specialized operations that read and/or write configuration data during execution of the user's logic function are possible.
In accordance with another aspect of the present invention, a cyclic redundancy check (CRC) register is connected to the bi-directional bus and to the packet processor. The CRC register performs transmission error detection functions based on the command/data transmissions to various registers connected to the bus, and based on the address information transmitted from the packet processor to the address/operand decoder, thereby detecting both errors in the data transmitted to a selected register, and errors in the destination of the data.
In accordance with another aspect of the present invention, a frame mask register is provided in the configuration memory that controls which memory cells of each frame (column) are written during a configuration operation, thereby allowing selective access to individual groups of configuration data stored in the memory array.


REFERENCES:
patent: Re. 34363 (1993-08-01), Freeman
patent: 5208781 (1993-05-01), Matsushima
patent: 5394031 (1995-02-01), Britton et al.
patent: 5426379 (1995-06-01), Trimberger
patent: 5457408 (1995-10-01), Leung
patent: 5485418 (1996-01-01), Hiraki et al.
patent: 5488582 (1996-01-01), Camarota
patent: 5670897 (1997-09-01), Kean
patent: 5773993 (1998-06-01), Trimberger
patent: 6034536 (2000-09-01), McCl

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