FPGA configuration bitstream encryption using modified key

Details FPGA configuration bitstream encryption using modified key FPGA configuration bitstream encryption using modified key

2011-07-19

2011-07-19

Zand, Kambiz (Department: 2434)

Electrical computers and digital processing systems: support

Multiple computer communication using cryptography

Packet header designating cryptographically protected data

C713S161000, C709S236000, C714S100000

Reexamination Certificate

active

07984292

ABSTRACT:
Circuits, methods, and apparatus that prevent detection and erasure of a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a user key in order to prevent its detection. In a specific embodiment, the user key is masked by software that performs a function on it a first number of times. The result is used to encrypt a configuration bitstream. The user key is also provided to an FPGA or other device, where the function is performed a second number of times and the result stored. When the device is configured, the result is retrieved, the function is performed on it the first number of times less the second number of times and then it is used to decrypt the configuration bitstream. A further embodiment uses a one-time programmable fuse (OTP) array to prevent erasure or modification.

REFERENCES:
patent: 5457408 (1995-10-01), Leung
patent: 6191614 (2001-02-01), Schultz et al.
patent: 7200235 (2007-04-01), Trimberger
patent: 7278128 (2007-10-01), Trimberger
patent: 7373668 (2008-05-01), Trimberger
patent: 2003/0020512 (2003-01-01), Mantey et al.

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