FPGA configurable logic block with multi-purpose logic/memory ci

Details FPGA configurable logic block with multi-purpose logic/memory ci FPGA configurable logic block with multi-purpose logic/memory ci

1999-02-25

2000-11-21

Tokar, Michael

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 41, 326 38, G06F 738

Patent

active

061508381

ABSTRACT:
A logic/memory circuit (LMC) utilized in a configurable logic block (CLB) of a programmable logic device (PLD) that implements an eight-input lookup table (LUT) using an array of programmable elements arranged in rows and columns. A decoder is used to read bit values from one column (e.g., sixteen programmable elements) of the array. In one embodiment, a separate read bit line is provided to facilitate faster read operations. A sixteen-to-one multiplexer/demultiplexer circuit is used to pass selected bit values to an output terminal. The array of programmable elements is programmable both from configuration lines during a configuration mode, and by data transmitted on the interconnect resources through the multiplexer/demultiplexer circuit. In one embodiment, the programmable elements of the array are connected in pairs to product term generation circuitry. Product terms generated by the product term circuitry are passed to a macrocell circuit to perform programmable array logic (PAL) logic operations. In another embodiment, a CLB includes four LMCs and a multiplier circuit such that large amounts of logic are locally implemented, thereby avoiding signal delays associated with transmission over general purpose interconnect resources within a PLD.

REFERENCES:
patent: 5362999 (1994-11-01), Chiang
patent: 5432719 (1995-07-01), Freeman et al.
patent: 5473267 (1995-12-01), Stansfield
patent: 5801547 (1998-09-01), Kean
patent: 5828229 (1998-10-01), Cliff et al.
patent: 6020759 (2000-02-01), Heile
"SMAP: Heterogenous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays", by Steve J. E. Wilton, published Feb. 1998, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays.

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