FPGA circuits and methods considering process variations

Details FPGA circuits and methods considering process variations FPGA circuits and methods considering process variations

2011-04-05

2011-04-05

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Testing or evaluating

C716S111000, C716S117000, C716S128000, C703S016000

Reexamination Certificate

active

07921402

ABSTRACT:
Methods are described herein which consider both die-to-die and within-die variations in effective channel length, threshold voltage, and gate oxide thickness, based on first developing closed-form models of chip level FPGA leakage and timing variations. Execution times are significantly reduced using these methods in comparison to performing detailed evaluation. The teachings provide mean and standard deviation which were found to be within 3% from those computed by Monte Carlo simulation, while leakage and delay variations can be up to 3× and 1.9×, respectively. Analytical yield models are derived which consider both leakage and timing variations, and use such models to evaluate FPGA device and architecture in response to process variations. The teachings allow improved modeling of leakage and timing yields and thus co-optimization to improve yield rates.

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