FPGA-based digital circuit for reducing readback time

Details FPGA-based digital circuit for reducing readback time FPGA-based digital circuit for reducing readback time

2007-09-18

2007-09-18

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

C326S041000, C326S047000

Reexamination Certificate

active

11190509

ABSTRACT:
An improved digital circuit for reducing readback time in field programmable gate arrays (FPGAs) includes a shift register having a plurality of latches and a clock and a reset signal provided to the latches. An interconnect circuit is provided between each pair of latches of the shift register for providing a selective data frame from the desired latch or latches. Connecting a control signal generator to a control input of said interconnect circuit enables quick readback of selected data frames, thereby reducing the time consumed for debugging of an FPGA.

REFERENCES:
patent: 5394031 (1995-02-01), Britton et al.
patent: 5426379 (1995-06-01), Trimberger
patent: 6069489 (2000-05-01), Iwanczuk et al.

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