Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...
Reexamination Certificate
2000-03-29
2001-12-04
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Having details of setting or programming of interconnections...
C326S047000
Reexamination Certificate
active
06326806
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to the configuration of field programmable gate arrays (FPGAs), and more particularly to an FPGA configured as a communications access point and reconfiguration of an FPGA via a communications channel.
BACKGROUND
Increasing numbers of Internet appliances (“appliances”) are appearing and supplanting some of the Internet accessibility functions that have traditionally been provided by personal computers/workstations (PCs). For example, individual appliances that provide email, music downloads, radio, and web browsing as well as other functions are presently available.
While such appliances typically do not exhibit the full range of hardware and software found on most PCs, they are often implemented in accordance with the same general architecture: a processor, a memory, an operating system, and an application program. The processor is generally highly optimized for arithmetic and data processing and includes an instruction processing pipeline and floating-point unit. However, many of the performance-enhancing features of the processor are unused during communication. The operating system is sometimes an adaptation of a general purpose operating system for a PC, with the appliance operating system not being fully optimized for network communications. Thus, the appliances may be relatively inexpensive to engineer, but inefficient in terms of resource utilization and performance.
Field programmable gate arrays (FPGAs) are frequently used in communications, data processing, data storage and other applications. The appealing characteristics of FPGAs are speed that approaches that of an application specific integrated circuit (ASIC) and programmability for design flexibility. As compared to a stored program processor arrangement, however, the re-programmability of an FPGA is less convenient. For example, to upgrade a program in a stored program processor arrangement, the operating system can be used to replace a program file. Thus, in the context of an Internet appliance, a program may be upgraded over the Internet. An FPGA, in contrast, generally requires special hardware to provide a configuration bitstream to the FPGA. Thus, while the speed of FPGAs provides an advantage for use in Internet appliances, the traditional methods for reconfiguring FPGAs have disadvantages.
A system and method that address the aforementioned problems, as well as other related problems, are therefore desirable.
SUMMARY OF THE INVENTION
An FPGA-based communications access point and system for reconfiguration of the FPGA via a communications channel are described in various embodiments. One embodiment of the invention includes a physical interface circuit (PHY), a storage element, an FPGA, and a configuration control circuit. The storage element can be, for example, a RAM, FIFO, disk drive, or flash memory. The physical interface circuit is arranged for connection to a communications channel and is coupled to the FPGA. (The communications channel may be a wired or wireless network, for example, a local area network, a wide area network, or the Internet.) The configuration control circuit includes a controlling circuit (e.g., a programmable logic device, or PLD) and a memory device (e.g., a PROM). The memory device is loaded with an initial configuration bitstream for the FPGA. The initial configuration bitstream implements both a communications protocol and a control function that writes configuration bits received by the FPGA via the communications channel to the storage element. (In some embodiments, other user functions or applications are also included in the initial configuration bitstream.) The control function also generates a reconfiguration signal responsive to a first predetermined condition. The controlling circuit is configured to load the initial configuration bitstream from the memory device into the FPGA (e.g., to “bootstrap” the FPGA, or configure the FPGA on powerup), and, responsive to the reconfiguration signal from the FPGA, to load a second configuration bitstream from the storage element into the FPGA. In another embodiment, the controlling circuit loads a third configuration bitstream from the memory device, and so forth. When the FPGA is partially reconfigurable, after the initial configuration step the reconfigurations from the memory device or the storage element may be full or partial reconfigurations, i.e., may provide configuration bitstreams to reconfigure all or part of the FPGA.
In one embodiment, the initial configuration bitstream is stored on a PROM or other memory device that is local relative to the board on which the FPGA is mounted. In another embodiment, the initial configuration bitstream is provided from an off-board source.
In another embodiment, where the FPGA is partially reconfigurable, the controlling circuit is implemented in the FPGA itself by the initial configuration bitstream. Thus, in this embodiment, the initial configuration bitstream implements: 1) a communications protocol; 2) a control node for passing new configuration data (received via the communications channel) from the FPGA to the storage element and for generating a reconfiguration signal; and 3) a controlling circuit responsive to the reconfiguration signal that uses the new configuration data stored in the storage element to partially reconfigure the FPGA. Optionally, a user application is also implemented by the initial configuration bitstream. In other embodiments, one or more user applications are supplied in the new configuration data via the communications channel. These self-reconfiguring embodiments require an additional bootstrapping circuit for initial configuration of the FPGA. For example, the bootstrapping circuit may include a PROM controlled by the FPGA using the well-known “master-slave” circuit structure and utilizing hard-wired circuits provided in the FPGA. These self-reconfiguring embodiments can be implemented, for example, in the Virtexm family of FPGAs available from Xilinx, Inc.
In another embodiment including self-reconfiguration of a partially reconfigurable FPGA, the storage element is implemented in the FPGA itself (for example, in block RAM resources of the FPGA) by the initial configuration bitstream. In this embodiment, reconfigurations from the storage element are always partial reconfigurations not affecting the FPGA resources used to implement the storage element. In one embodiment, both the storage element and the controlling circuit are implemented in the FPGA.
Thus, the invention provides systems and methods by which an FPGA can be reconfigured via a communications channel using standard communications protocols, and without the intervention of a processor or network server at the FPGA site.
It will be appreciated that various other embodiments are set forth in the Detailed Description and Claims that follow.
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Xilinx Application Note by Carl Carmichael, “Configuring Virtex FPGAs from Parallel EPROMs with a CPLD”, XAPP 137 (Version 1.0) Mar. 1, 1999, pp. 1-7.
Fallside Hamish T.
Smith Michael J. S.
Chang Daniel D.
Maunu LeRoy D.
Tokar Michael
Xilinx , Inc.
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