FPGA architecture with repeatable tiles including routing matric

Details FPGA architecture with repeatable tiles including routing matric FPGA architecture with repeatable tiles including routing matric

1996-03-19

1997-10-28

Westin, Edward P.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 39, H03K 19177

Patent

active

056821077

ABSTRACT:
An FPGA architecture offers logic elements with direct connection to neighboring logic elements and indirect connection through a routing matrix. A logic element and a portion of the routing matrix are formed as part of a tile, and tiles are joined to form arrays of selectable size. The routing matrix includes routing lines which connect just from one tile to the next and routing lines which extend longer distances through several tiles or through the entire chip. This combination is achieved by the formation of individual tiles, all of which are identical.

REFERENCES:
patent: Re34363 (1993-08-01), Freeman
patent: 4124899 (1978-11-01), Birkner et al.
patent: 4642487 (1987-02-01), Carter
patent: 4706216 (1987-11-01), Carter
patent: 4750155 (1988-06-01), Hsieh
patent: 4758745 (1988-07-01), Elgamal et al.
patent: 4821233 (1989-04-01), Hsieh
patent: 4870302 (1989-09-01), Freeman
patent: 5079451 (1992-01-01), Gudgen et al.
patent: 5122685 (1992-06-01), Chan et al.
patent: 5144166 (1992-09-01), Camarota et al.
patent: 5148390 (1992-09-01), Hsieh
patent: 5157618 (1992-10-01), Ravindra et al.
patent: 5198705 (1993-03-01), Galbraith et al.
patent: 5208491 (1993-05-01), Ebeling et al.
patent: 5241224 (1993-08-01), Pedersen et al.
patent: 5243238 (1993-09-01), Kean
patent: 5258668 (1993-11-01), Cliff et al.
patent: 5260610 (1993-11-01), Pedersen et al.
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5260881 (1993-11-01), Agrawal et al.
patent: 5267187 (1993-11-01), Hsieh et al.
patent: 5280202 (1994-01-01), Chan et al.
patent: 5313119 (1994-05-01), Cooke et al.
patent: 5319255 (1994-06-01), Gaverick et al.
patent: 5323069 (1994-06-01), Smith, Jr.
patent: 5333279 (1994-07-01), Dunning
patent: 5343406 (1994-08-01), Freeman et al.
patent: 5347519 (1994-09-01), Cooke et al.
patent: 5349250 (1994-09-01), New
patent: 5455525 (1995-10-01), Ho et al.
patent: 5457410 (1995-10-01), Ting
patent: 5500609 (1996-03-01), Kean
patent: 5546596 (1996-08-01), Geist
Weste et al.; "Principles of CMOS VLSI: A Systems Approach"; copyright 1985 by AT&T Bell Laboratories, Inc. and Kamran Eshraghian; p. 56.
Morales, Luis, "Boundary Scan in XC4000 Devices", XAPP 017.001, October 1992, pp. 2-108 and 2-180.

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