Static information storage and retrieval – Read/write circuit – Serial read/write
Patent
1998-08-12
2000-05-23
Nguyen, Tan T.
Static information storage and retrieval
Read/write circuit
Serial read/write
36518902, G11C 700
Patent
active
060672676
ABSTRACT:
A FIFO memory apparatus of the present invention includes an array of registers including a plurality of stacked subarrays. A first plurality of multiplexers is provided including one multiplexer for receiving data from each one of the subarrays. A second plurality of multiplexers is also provided each for receiving data from two other multiplexers. One of the second plurality of multiplexers supplies an output for the FIFO memory apparatus, while each of the others, in pairs, supply other multiplexers of the apparatus. The invention uses a four-way interleaved memory architecture for pre-decoding the FIFO read pointer and driving out data from one of the sixteen deep 32-bit wide registers, in advance. In this way, the final stage of the timing critical path is from the Q output of a toggle flip-flop to a two-to-one multiplexer and output buffer. This Q output of the toggle flip-flop is the least significant bit (LSB) of a four-bit counter used to select one of the 16-bit deep, 32-bit wide registers of the FIFO.
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Nguyen Tan T.
Toshiba America Electronic Components Inc.
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