Four transistor static-random-access-memory cell

Details Four transistor static-random-access-memory cell Four transistor static-random-access-memory cell

2001-07-26

2003-11-11

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S288000

Reexamination Certificate

active

06646310

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a four-transistor static-random-access-memory (SRAM) memory cell that is suitable for application to the lower power product, that has a reduced size as compared with conventional SRAM cells, or both.
2. Description of the Prior Art
To meet customer demand for small size and low power products, manufacturers are producing newer integrated circuits (ICs) that operate with lower supply voltages and that include smaller internal subcircuits such as memory cells. Many ICs, such as memory circuits or other circuits such as microprocessors that include onboard memory, include one or more SRAM cells for data storage. SRAMs cells are popular because they operate at a higher speed than dynamic random-access-memory (DRAM) cells, and as long as they are powered, they can store data indefinitely, unlike DRAM cells, which must be periodically refreshed.
The conventional structure of the SRAM cell is a six-transistors SRAM cell, which means six transistors are used to form a SRAM cell. In general, advantages of six-transistor SRAM cell at least include high speed and the possibility of low supply voltage. Unfortunately, one unavoidable disadvantage is that the area of the six-transistor SRAM cell is large. Clearly, when the size of the semiconductor device is continually decreased, the disadvantage is more serious and it is desired to overcome the disadvantage by either improving the structure of the six-transistor SRAM cell or providing a new SRAM cell.
One way to reduce the area of the six-transistor SRAM cell is to make the structure three-dimensional. However, the solid structure of the six-transistor SRAM cell also complicates relative fabrication and configuration of the six-transistor SRAM cell. In other words, this way is not an efficient way to overcome the disadvantages of known devices.
Another popular way to reduce the area of six-transistor SRAM cell is the application of a four-transistor SRAM. Although there are numerous varieties of four-transistor SRAM cell, the basic structure of the four-transistor SRAM cell can be divided into two access transistors and two pull-down transistors. Herein, as usual, one access transistor and one pull-down transistor are used to store data, another access transistor and another pull-down transistor are used to control reading/writing processes. Clearly, owing to the number of transistors being used is decreased, the occupied area of four-transistor SRAM cell is less than that of the six-transistor SRAM cell. Thus, the four-transistor SRAM cell is more suitable for ICs whenever sizes of ICs are reduced. Even four-transistors also meet some disadvantages such as higher off-state leakage current of PMOS. More introduction of four-transistor SRAM cell can be provided by referring to U.S. Pat. Nos. 5,943,269, 6,091,628, 6,044,011, 6,011,726, and 5,751,044.
One ordinary circuit diagram of four-transistor SRAM cell is shown in FIG.
1
. The four-transistor SRAM cell, which is a loadless four-transistors SRAM cell, comprises first transistor
11
, second transistor
12
, third transistor
13
, fourth transistor
14
, first word line terminal
15
, second word line terminal
16
, first bit line terminal
17
and second bit line terminal
18
. In detail, source of first transistor
11
is coupled to first bit line terminal
17
, gate of first transistor
11
coupled to first word line terminal
15
, drain of first transistor
11
is coupled to gate of fourth terminal
14
, source of second transistor
12
is coupled to second bit line terminal
18
, gate of second transistor is coupled to second word line terminal
16
, drain of second transistor
12
is coupled to gate to third transistor
13
. More over, drain of fourth transistor
14
and drain of third transistor
13
are coupled to a common voltage point
19
, such as electrical zero point, each of both first bit line terminal
17
and second bit line terminal
18
is coupled to a corresponding bit line, and both first word line terminal
15
and second word line terminal
16
are coupled to the same word line.
Because leakage current of first transistor
11
and leakage current of second transistor
12
are not absolute zero, especially when first transistor
11
/second transistor
12
are P-type transistor. An unavoidable shortage is that because first word line terminal
15
and second word line terminal
16
by same word line, third transistor
13
is turn on by leakage current of second transistor
12
whenever both first transistor
11
and second transistor
12
are not totally turn off. Thus, whenever current is sent to first bit line terminal
17
(means data is storaged), owing to both first transistor
11
and third transistor
13
are not totally turn off now, current continually flow through first transistor
11
and third transistor into common voltage point
19
. Significantly, continuous flow of current requires continuous supply of current, then stand-by current of the four-transistor SRAM cell is not negligible and the four-transistor SRAM cell is less suitable for low power product.
Therefore, although the four-transistor SRAM is physically smaller and is suitable for some ICs that include smaller internal subcircuits, it still is not suitable for operation at low supply power. Improvement of the four-transistor SRAM is desired to make it suitable for a low power product.
SUMMARY OF THE INVENTION
One main object of the invention is to present a four-transistor SRAM cell which is suitable for a low power product.
Another important object of the invention is to present a four-transistor SRAM cell which is easy to be produce, especially the differences between the present four-transistor SRAM cells and other well-known four-transistor SRAM cells are not too large to let fabrication of the present four-transistor SRAM cell be strongly different from fabrication of the well-known four-transistor SRAM cell.
Still an essential object of the invention is to present a four-transistor SRAM cell by limiting the circuit diagram of the present four-transistor SRAM cell but not limiting the structure of the present four-transistor SRAM cell. In other words, there are various structures of the present four-transistor SRAM cell.
One embodiment of the invention is a memory cell, a four-transistor SRAM cell, which comprises the following elements: a first word line terminal, a second word line terminal, a first bit line terminal, a second bit line terminal, a first transistor, a second transistor, a third transistor, and a fourth transistor. The gate of the first transistor is coupled to the first word line terminal and the source of the first transistor is coupled to the first bit line terminal, the gate of the second transistor is coupled to the second word line terminal and the source of the second transistor is coupled to the second bit line terminal, the source of the third transistor is coupled to the drain of the first transistor and the gate of the third transistor is coupled to the drain of the second transistor, the source of the fourth transistor is coupled to the drain of the second transistor and the gate of the fourth transistor is coupled to the drain of the first transistor.


REFERENCES:
patent: 4780751 (1988-10-01), Nishimoto
patent: 4916668 (1990-04-01), Matsui
patent: 5373189 (1994-12-01), Massit et al.
patent: 5440513 (1995-08-01), Smith
patent: 5486717 (1996-01-01), Kokubo et al.

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