Four state two bit recoded alignment fault state circuit for mic

Details Four state two bit recoded alignment fault state circuit for mic Four state two bit recoded alignment fault state circuit for mic

1995-06-07

1997-09-09

Kim, Matthew M.

Electrical computers and digital processing systems: memory

Address formation

Slip control, misaligning, boundary alignment

711220, 711215, G06F 1200

Patent

active

056665083

ABSTRACT:
An apparatus for controlling address alignment fault generation employing a recoded two bit structure. This alignment fault state circuit stores one of four states corresponding to whether the operating system permits address misalignment fault generation and whether the application program requests such address misalignment fault generation. The two latches each hold either a first state or a second state. Together the two latches have either a first combined state, a second combined state, a third combined state or a fourth combined state. The two latches have a recoded set of states such that receipt of at least one of the alignment check on instruction, the alignment check off instruction, the alignment mask permit instruction or the alignment mask prohibit instruction causes both latches to change state. An output circuit generates an alignment fault qualifier signal enabling generation of an address alignment fault signal if the two latches has a predetermined one of said first, second, third or fourth combined state. An alignment detector receives an indication of the selected data size and the least significant bits of the generated address which is ANDed with the alignment fault qualifier signal to produce an alignment fault signal.

REFERENCES:
patent: 4124891 (1978-11-01), Weller, III et al.
patent: 4972338 (1990-11-01), Crawford et al.
patent: 5319769 (1994-06-01), Muramatsu
patent: 5440710 (1995-08-01), Richter et al.
patent: 5519842 (1996-05-01), Atallah et al.

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