Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2005-06-28
2005-06-28
Myers, Paul R. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S109000, C710S110000, C710S220000, C710S309000, C711S151000
Reexamination Certificate
active
06912609
ABSTRACT:
A four-phase arbitration system employs a master and a slave arbiter. The master arbiter operates to provide ownership of a bus to a first device if a second device, coupled to the slave arbiter is not conducting a transaction. If the second device desires use of the bus, the slave arbiter sends a request to the master arbiter, which asserts an acknowledge signal for as long as the first device has ownership of the bus, and at least as long as a timeout of the first device. The master arbiter de-asserts its acknowledge signal when the first device ceases ownership of the bus. The slave arbiter is responsive to the de-assertion of the acknowledge signal to assert bus ownership to the second device. When the second device transaction is completed, its request signal is de-asserted to the master arbiter, causing the master arbiter to re-assert the acknowledge signal. Failure to receive a de-asserted acknowledge signal causes the slave arbiter to move to the next state.
REFERENCES:
patent: 5682467 (1997-10-01), Ambalavanar
patent: 5805838 (1998-09-01), Sutherland et al.
patent: 5923859 (1999-07-01), Melo et al.
patent: 6259984 (2001-07-01), Kanzaki et al.
patent: 6430651 (2002-08-01), Isobe
Giles Christopher M.
Sluiter David O.
Stuber Russell B.
LSI Logic Corporation
Myers Paul R.
Phan Raymond N
Westman Champlin & Kelly
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