Forwarded clock recovery with variable latency

Details Forwarded clock recovery with variable latency Forwarded clock recovery with variable latency

1998-07-17

2002-07-09

Corrielus, Jean (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

Reexamination Certificate

active

06418176

ABSTRACT:

BACKGROUND OF THE INVENTION
Clock forwarding is a technique that allows circuits to transfer data at high speeds. Clock forwarding involves sending more than one bit of data through each conductor of a data path in a single cycle of a clock signal, and providing the clock signal through a separate conductor such that it accompanies the data. In contrast, synchronous point-to-point communication involves sending a single bit of data through each data path conductor in a single cycle of a clock signal. As a result, the bandwidth of forwarded clock circuits is typically higher than that of synchronous point-to-point circuits.
Clock forwarding is useful in situations where the number of data path conductors is limited. For example, the specifications for an integrated circuit (IC) chip set may limit the number of data path pins that are available on certain ICs. In such a situation, the IC designers may include forwarded clock circuitry within particular ICs to allow those ICs to transfer multiple bits through each of their data path pins during a single clock cycle. Such an arrangement may reduce the effect of, or even eliminate, any data transfer bottleneck caused by the limited availability of data path pins.
In an IC that transmits data using clock forwarding (i.e., a transmit IC), multiple forwarded clock transmit circuits provide information signals through respective data path pins, and forwarded clock signals through respective forwarded clock pins. The information signals contain data synchronously with edges of the forwarded clock signals.
In an IC that receives data using clock forwarding (i.e., a receive IC), multiple forwarded clock receive circuits receive information signals through respective data path pins, and forwarded clock signals through respective forwarded clock pins. A typical forwarded clock receive circuit includes a receive stage that receives an information signal synchronously with a forwarded clock signal, and a recovery stage that recovers data contained within the information signal synchronously with a recovery clock signal (e.g., an internal clock signal of the receive IC). The receive stage is generally driven by the forwarded clock signal, and thus operates in a forwarded clock domain. In contrast, the recovery stage is generally driven by the recovery clock signal, and thus operates in a recovery clock domain. The recovery clock signal and the forwarded clock signal are independent of each other, but typically have the same frequency and edges that closely coincide.
It is common for IC designers to design forwarded clock ICs such that they operate properly at a number of different clock speeds (rates or frequencies). IC designers often know ahead of time the maximum clock speeds of the recovery clock signal that is to drive the recovery stages of the multiple forwarded clock receive circuits, and thus make design decisions with this maximum clock speed in mind. In particular, IC designers typically consider the maximum clock speed of the recovery clock signal to be the optimal clock rate for their designs, and optimize their designs (e.g., select critical tolerances and features of the IC) such that data is recovered with minimal time latency when the recovery clock signal is at the optimal rate.
SUMMARY OF THE INVENTION
A conventional forwarded clock receive circuit, which is optimized to recover data with minimal latency when the recovery clock signal has an optimal rate, typically operates properly when the recovery clock signal has a sub-optimal rate. In particular, when the recovery clock signal is at the sub-optimal rate, the recovery stage may perform identical operations in the same number of cycles such that the cycle latency remains the same. However, since the cycle length of the recovery clock signal is longer at the sub-optimal rate, the time latency for recovering the data is longer.
In contrast, an embodiment of the present invention enables data to be recovered with different cycle latencies when the recovery clock signal has different rates. The embodiment is directed to a technique for providing data from an information signal. The technique involves receiving the information signal in the forwarded clock device synchronously with a forwarded clock signal. The technique further involves recovering data contained within the information signal synchronously with a recovery clock signal such that the data is recovered with (I) a particular cycle latency when the recovery clock signal has an optimal rate for the forwarded clock device, and (ii) a different cycle latency when the recovery clock signal has a sub-optimal rate.
Preferably, the particular cycle latency includes more cycles than the different cycle latency. As such, the time latency may be shorter when the recovery clock signal has the sub-optimal rate. The shorter latency results in quicker response time by circuits that further process the recovered data. In one embodiment, the particular cycle latency is one cycle longer than the different cycle latency.
The forwarded clock device may include a receive buffer that receives the information signal synchronously with the forwarded clock signal, and a delay buffer. In this situation, recovering the data preferably involves transferring contents of the receive buffer to the delay buffer synchronously with the recovery clock signal. Furthermore, recovering the data preferably involves reading exclusively from the delay buffer to capture the data contained within the information signal when the recovery clock signal has the optimal rate, and selectively reading from the delay buffer and the receive buffer to capture the data contained within the information signal when the recovery clock signal has the sub-optimal rate.
Another embodiment of the invention is directed to a technique for providing data from an information signal involving buffers. In particular, the technique involves receiving the information signal in a receive buffer synchronously with a forwarded clock signal, and transferring contents of the receive buffer to a delay buffer synchronously with a recovery clock signal. The technique further involves selectively reading from the receive buffer and the delay buffer to form a recovered signal that is synchronous with the recovery clock signal, the recovered signal having the data contained within the information signal.
Preferably, the receive buffer includes multiple storage elements such that selectively reading from the receive buffer involves selecting and reading from an element of the receive buffer to recover the data with minimal latency. A multiplexer may be interconnected between an output of the receive buffer and an input of the delay buffer. In this situation, selecting and reading from the element may involve sampling at the output of the receive buffer to circumvent the multiplexer. Alternatively, selecting and reading may involve sampling at the input of the delay buffer to include a signal delay caused by the multiplexer.


REFERENCES:
patent: 4811364 (1989-03-01), Sager et al.
patent: 4979190 (1990-12-01), Sager et al.
patent: 5003537 (1991-03-01), Sager
patent: 5923613 (1999-07-01), Tien et al.

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