Forming vias using sacrificial material

Details Forming vias using sacrificial material Forming vias using sacrificial material

2007-06-29

2010-06-01

Nguyen, Ha Tran T (Department: 2829)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S618000, C257SE21585, C257SE21587

Reexamination Certificate

active

07727886

ABSTRACT:
In one embodiment, the present invention includes a method for forming a sacrificial material layer, patterning it to obtain a first patterned sacrificial material layer, embedding the first patterned sacrificial material layer into a dielectric material, treating the first patterned sacrificial material layer to remove it to thus provide a patterned dielectric layer having a plurality of openings in which vias may be formed. Other embodiments are described and claimed.

REFERENCES:
patent: 2008/0070349 (2008-03-01), Matayabas et al.
patent: 2008/0160177 (2008-07-01), Mataybas et al.
U.S. Appl. No. 11/533,653, filed Sep. 20, 2006, entitled “Formation of Holes in Substrates Using Dewetting Coatings,” by James C. Matayabas, Jr., et al.
U.S. Appl. No. 11/618,528, filed Dec. 29, 2006, entitled “Methods for Electroless Plating of Metal Traces on a Substrate and Devices and Systems Thereof,” by J. C. Mataybas, Jr., et al.

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