Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2006-02-02
2010-06-15
Tran, Thien F (Department: 2895)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S455000, C438S458000, C438S459000
Reexamination Certificate
active
07736988
ABSTRACT:
A method for forming a relaxed or pseudo-relaxed useful layer on a substrate is described. The method includes growing a strained semiconductor layer on a donor substrate, bonding a receiver substrate to the strained semiconductor layer by a vitreous layer of a material that becomes viscous above a certain viscosity temperature to form a first structure. The method further includes detaching the donor substrate from the first structure to form a second structure comprising the receiver substrate, the vitreous layer, and the strained layer, and then heat treating the second structure at a temperature and time sufficient to relax strains in the strained semiconductor layer and to form a relaxed or pseudo-relaxed useful layer on the receiver substrate.
REFERENCES:
patent: 5461243 (1995-10-01), Ek et al.
patent: 5882987 (1999-03-01), Srikrishnan
patent: 5906951 (1999-05-01), Chu et al.
patent: 6059895 (2000-05-01), Chu et al.
patent: 6100166 (2000-08-01), Sakaguchi et al.
patent: 6352942 (2002-03-01), Luan et al.
patent: 6524935 (2003-02-01), Canaperi et al.
patent: 6573126 (2003-06-01), Cheng et al.
patent: 6633066 (2003-10-01), Bae et al.
patent: 2002/0072130 (2002-06-01), Cheng et al.
patent: 2002/0146892 (2002-10-01), Notsu et al.
patent: 2002/0168864 (2002-11-01), Cheng et al.
patent: 2003/0003679 (2003-01-01), Doyle et al.
patent: 2003/0013305 (2003-01-01), Sugii et al.
patent: 2003/0155568 (2003-08-01), Cheng et al.
patent: 2003/0168654 (2003-09-01), Cheng et al.
patent: 101 00 194 (2001-07-01), None
patent: 1 248 294 (2002-10-01), None
patent: 2 818 010 (2002-06-01), None
patent: WO 99/53539 (1999-10-01), None
patent: WO 02/15244 (2002-02-01), None
patent: WO 02/43153 (2002-05-01), None
patent: WO 02/47156 (2002-06-01), None
J.-P. Colinge, “Silicon-on-Insulator Technology: Materials to VLSI, 2nd Edition,” Kluwer Academic Publishers, pp. 50-51. no date.
K.D. Hobart et al., “Compliant Substrates: A Comparative Study of the Relaxation Mechanisms of Strained Films Bonded to High and Low Viscosity Oxides,” Journal of Electronic Materials, 29:897-900 (2000).
B. Hollander et al., “Strain relaxation of pseudomorphic Si1-xGex/si(100) heterostructures after hydrogen or helium ion implantation for virtual substrate fabrication,” Nuclear Instruments and Methods in Physics Research B, 175-177:357-367 (2001).
S. Mantl et al., “Strain relaxation of epitaxial SiGe layers on Si(100) improved by hydrogen implantation,” Nuclear Instruments and Methods in Physics Research B, 147:29-34 (1999).
F. Schaffler, “High mobility Si and Ge Structures,” Semicond. Sci. Technol., 12:1515-1549 (1997).
T. Tezuka et al., “High-performance Strained Si-on-Insulator MOSFETs by Novel Fabrication Processes Utilizing Ge-Condensation Technique,” Symposium on VLSI Technology Digest of Technical Papers, pp. 96-97 (2002).
Q.-Y. Tong et al., Extracts of “Semiconductor on Wafer Bonding: Science and Technology”, John Wiley & Sons, Inc. no date.
Arene Emmanuel
Ghyselen Bruno
Mazure Carlos
S.O.I.Tec Silicon on Insulator Technologies
Tran Thien F
Winston & Strawn LLP
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