Forming local interconnects in integrated circuits

Details Forming local interconnects in integrated circuits Forming local interconnects in integrated circuits

1997-12-05

2000-04-18

Chaudhuri, Olik

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257380, 257379, H01L 2348, H01L 2352, H01L 2940

Patent

active

060518812

ABSTRACT:
A method and the resulting device to permit the formation of minimal insulating space between polysilicon gates by forming an insulating layer over the polysilicon gates and protecting selected ones of the gates and the insulating layer with an etch barrier so that the opening for local interconnect metallization can be misaligned and the selected gates will be protected by its etch barrier and not be exposed to the opening. Further, local interconnect conductive material can pass over a gate or unrelated resistor without shorting the gate/resistor.

REFERENCES:
patent: 5246882 (1993-09-01), Hartmann
patent: 5291058 (1994-03-01), Samata et al.
patent: 5320975 (1994-06-01), Cederbaum et al.
patent: 5385857 (1995-01-01), Solo De Zaldivar
patent: 5479054 (1995-12-01), Tottori
patent: 5482894 (1996-01-01), Havemann
patent: 5663086 (1997-09-01), Rostoker et al.

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