Forming a structure on a wafer

Details Forming a structure on a wafer Forming a structure on a wafer

2002-01-10

2003-10-28

Thompson, Craig (Department: 2813)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

Reexamination Certificate

active

06638870

ABSTRACT:

TECHNICAL FIELD
This invention relates to semiconductor manufacturing processes and in particular fabricating structures on a wafer.
BACKGROUND
With wafer level packaging (WLP), semiconductor manufacturing processes test and burn-in integrated circuits (ICs) at a wafer level instead of testing and burning-in the ICs in individual form. Such wafer level test (WLT) and wafer level burn-in (WLBI) typically place the wafers on test boards. Yet, in WLP, additional features such as rerouting layers may be fabricated on top of the substrate. These rerouting layers are delicate and fragile features. A compression stop is mounted on top of the wafer and protects the interconnect elements during test, burn-in, and handling. The physical protection of the compression stop blocks or stops any further compression of compliant elements. Historically, a soft or hard passivation layer deposited on the last metal layer protected the IC during fabrication.
Compliant structures are used to reduce thermal and mechanical stresses between the wafer and the test board and to assist in providing electrical interconnects so that the ICs can be tested while in wafer form. Since compliant structures are elastic, they can be moved in up to three-dimensions. In other words, in a raised temperature environment, compliant structures decouple the stress when a wafer and a test board expand at different rates due to the different coefficients of thermal expansion between the test board and the wafer.
Typically, a method of forming a compression stop, a compliant element, and a rerouting on a wafer requires at least three photolithographic processing steps.
SUMMARY
The invention is directed to a method for fabricating structures on an integrated circuit (IC). In particular, the invention relates to forming a compression stop, a rerouting layer, and a compliant element on the surface of the wafer using one photolithographic step. The method includes providing a material onto a surface of the wafer and shaping to have a shape corresponding to the structure.
This method may also include one or more of the following embodiments. The method includes depositing the material (e.g., silicone, polyethylene, polypropylene, polyimid, epoxy, a dielectric, etc.) onto a wafer. In other embodiments, the method includes depositing a seed layer onto the wafer and the material and depositing a photoresist on the wafer. Still other embodiments include depositing a metal layer on top of the seed layer, removing the photoresist, etching the seed layer, and etching the material. In other embodiments, the structure is a compression stop, a compliant element, or a rerouting layer or a combination thereof.
In other embodiments the method includes printing the material onto the surface of the wafer. In other embodiments, the shaping of the material includes embossing the material. In other embodiments, shaping the material includes printing the material on the surface of the wafer more than once. In still other embodiments, the method includes soldering the structure to a board.
Among other advantages, the method of the invention uses only one photolithographic step to create the compression stop, compliant element and the rerouting layer. In addition, this method allows a compression stop to be mounted in any location on the wafer.


REFERENCES:
patent: 5734547 (1998-03-01), Iversen
patent: 5937758 (1999-08-01), Maracas et al.
patent: 6147401 (2000-11-01), Solberg
patent: 6337445 (2002-01-01), Abbott et al.

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