Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1997-11-05
1999-11-16
Niebling, John F.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438592, 438595, 438649, H01L 213205
Patent
active
059857447
ABSTRACT:
A method for fabricating a semiconductor device includes forming a plurality of field oxide layers on a semiconductor substrate to define an active region; forming a plurality of gate electrodes each having sidewall spacers on the active region of the semiconductor substrate, depositing a metal layer on the semiconductor substrate including the plurality of gate electrodes, defining a first region and a second region, removing the metal layer over the second region, and forming a silicide layer on the gate electrode and on the semiconductor substrate over the first region with a first annealing process.
REFERENCES:
patent: 4478679 (1984-10-01), Chang et al.
patent: 4563805 (1986-01-01), Scovell et al.
patent: 5240872 (1993-08-01), Motonami et al.
patent: 5338702 (1994-08-01), Kobeda et al.
patent: 5589417 (1996-12-01), Jeng
patent: 5635426 (1997-06-01), Hayashi et al.
patent: 5736421 (1998-04-01), Shimomura et al.
patent: 5766991 (1998-06-01), Chen
Wolf, S., "Silicon Processing for the VLSI Era Vol. 2--Process Integration" pp. 147-152, 1990.
Hack Jonathan
LG Semicon Co. Ltd.
Niebling John F.
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