Forming a semi-recessed metal for better EM and Planarization us

Fishing – trapping – and vermin destroying

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437195, 437228, 437981, H01L 2128

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active

055853072

ABSTRACT:
A new method of metallization for improved electromigration performance of an integrated circuit is described. An insulating layer is deposited overlying semiconductor device structures. A shallow trench is etched into the insulating layer where a conducting line is to be formed. A contact opening is etched through the insulating layer within the shallow trench to the underlying semiconductor device structures. A conducting layer is deposited overlying the insulating layer, within the shallow trench, and within the contact opening wherein the conducting layer is partially buried within the insulating layer within the shallow trench. Planarization is improved because of the reduced step height of the conducting layer. The improved planarization and reduced step height result in improved electromigration performance.

REFERENCES:
patent: 4789648 (1988-12-01), Chow et al.
patent: 4931410 (1990-06-01), Tokunaga et al.
patent: 5086017 (1992-02-01), Lu
patent: 5441916 (1995-08-01), Motonami
"Silicon Processing for the VLSI Era, vol. 1", S. Wolf, Lattice Press 1986, pp. 418-423, 477.
"Silicon Processing for the VLSI Era, vol. 2", S. Wolf, Lattice Press, 1990, p. 229.

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