Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2007-09-12
2010-12-14
Landau, Matthew C (Department: 2813)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C257SE21249
Reexamination Certificate
active
07851366
ABSTRACT:
The invention relates to a method of realization of a sacrificial layer, including the steps of:lithography of a resin deposited on a substrate in order to supply a lithographed resist pattern on a substrate zone, the zone having a given size and a given form, the pattern occupying a given volume,annealed according to a thermal cycle of the lithographed resist pattern,the method being characterised in that it includes, according to the resin, the determination of the size and of the form of said zone of the substrate, and the determination of the volume of the resin deposited on said zone so that the thermal cycle annealing supplies a profile chosen from among the following profiles: a planarising domed profile and a “double air gap” profile.
REFERENCES:
patent: 2005/0227428 (2005-10-01), Mihai et al.
patent: WO 03/078299 (2003-09-01), None
Sofiane Soulimane, et al., “Polymeric material sacrificial layer for MEMS fabrication”, Nanofun-Poly International Conference, XP-002432492, May 31, 2006, 2 pages.
A. J. Gallant, et al., “Sacrificial layers for Widely tunable capacitors”, IEE Proceedings Science Measurement and Tehcnology, vol. 151, No. 2, XP-006021520, Mar. 3, 2004, pp. 104-109.
Casset Fabrice
Soulimane Sofiane
Commissariat A l'Energie Atomique
Landau Matthew C
McCall-Shepard Sonya D
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
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