Formation without vacuum break of sacrificial layer that...

Details Formation without vacuum break of sacrificial layer that... Formation without vacuum break of sacrificial layer that...

2002-01-17

2002-12-24

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S687000, C438S644000, C438S645000, C438S678000, C438S627000, C438S628000, C438S648000

Reexamination Certificate

active

06498093

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to fabrication of interconnect structures within integrated circuits, and more particularly, to formation of a sacrificial layer on an underlying material within an interconnect opening without a vacuum break, with the sacrificial layer dissolving away in an acidic activation solution used for formation of a catalytic seed layer on the underlying material.
BACKGROUND OF THE INVENTION
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Thus far, aluminum has been prevalently used for metallization within integrated circuits. However, as the width of metal lines are scaled down to smaller submicron and even nanometer dimensions, aluminum metallization shows electromigration failure. Electromigration failure, which may lead to open and extruded of metal lines, is now a commonly recognized problem. Moreover, as dimensions of metal lines further decrease, metal line resistance increases substantially, and this increase in line resistance may adversely affect circuit performance.
Given the concerns of electromigration and line resistance with smaller metal lines and vias, copper is considered a more viable metal for smaller metallization dimensions. Copper has lower bulk resistivity and potentially higher electromigration tolerance than aluminum. Both the lower bulk resistivity and the higher electromigration tolerance improve circuit performance.
Referring to
FIG. 1
, a cross sectional view is shown of a copper interconnect
102
within a trench
104
formed in an insulating layer
106
. The copper interconnect
102
within the insulating layer
106
is formed on a semiconductor wafer
108
such as a silicon substrate as part of an integrated circuit. Because copper is not a volatile metal, copper cannot be easily etched away in a deposition and etching process as typically used for aluminum metallization. Thus, the copper interconnect
102
is typically formed by etching the trench
104
as an opening within the insulating layer
106
, and the trench
104
is then filled with copper typically by an electroplating process, as known to one of ordinary skill in the art of integrated circuit fabrication.
Unfortunately, copper is a mid-bandgap impurity in silicon and silicon dioxide. Thus, copper may diffuse easily into these common integrated circuit materials. Referring to
FIG. 1
, the insulating layer
106
may be comprised of silicon dioxide or a low dielectric constant insulating material such as organic doped silica, as known to one of ordinary skill in the art of integrated circuit fabrication. The low dielectric constant insulating material has a dielectric constant that is lower than that of pure silicon dioxide (SiO
2
) for lower capacitance of the interconnect, as known to one of ordinary skill in the art of integrated circuit fabrication.
Copper may easily diffuse into such an insulating layer
106
, and this diffusion of copper may degrade the performance of the integrated circuit. Thus, a diffusion barrier material
110
is deposited to surround the copper interconnect
102
within the insulating layer
106
on the sidewalls and the bottom wall of the copper interconnect
102
, as known to one of ordinary skill in the art of integrated circuit fabrication. The diffusion barrier material
110
is disposed between the copper interconnect
102
and the insulating layer
106
for preventing diffusion of copper from the copper interconnect
102
to the insulating layer
106
to preserve the integrity of the insulating layer
106
.
Further referring to
FIG. 1
, an encapsulating layer
112
is deposited as a passivation layer to encapsulate the copper interconnect
102
, as known to one of ordinary skill in the art of integrated circuit fabrication. The encapsulating layer
112
is typically comprised of a dielectric such as silicon nitride, and copper from the copper interconnect
102
does not easily diffuse into such a dielectric of the encapsulating layer
112
.
Referring to
FIG. 2
, typically for filling the trench
104
with copper, the diffusion barrier material
110
is deposited on the sidewalls and the bottom wall of the trench
104
. When the diffusion barrier material
110
is exposed to oxygen, such as oxygen gas in air for example, the diffusion barrier material
110
may oxidize to form an undesired oxide layer
120
. For example, when the diffusion barrier material
110
is comprised of tantalum, the undesired oxide layer
120
is comprised of tantalum oxide (Ta
2
O
5
) that is formed from oxidation of the exposed surfaces of the diffusion barrier material
110
.
Referring to
FIG. 3
, before electroless deposition of copper for filling the trench
104
, a catalytic seed layer
122
is deposited on any exposed surfaces. With formation of the undesired oxide layer
120
, the catalytic seed layer
122
is deposited on the undesired oxide layer
120
. Referring to
FIG. 4
, the copper fill
124
is electrolessly deposited from the catalytic seed layer
122
to fill the trench opening
104
. Referring to
FIG. 5
, the portions of the copper fill
124
, the catalytic seed layer
122
, the undesired oxide layer
120
, and the diffusion barrier material
110
disposed on the surrounding insulating layer
106
are polished away in a CMP (chemical mechanical polishing) process such that the copper fill
124
, the catalytic seed layer
122
, the undesired oxide layer
120
, and the diffusion barrier material
110
are contained within the trench
104
.
In the prior art interconnect structure as illustrated in
FIGS. 2
,
3
,
4
, and
5
, the undesired oxide layer
120
disposed between the diffusion barrier material
110
and the catalytic seed layer
122
degrades the performance of the interconnect structure. The catalytic seed layer
122
may have poor adhesion to the undesired oxide layer
120
to promote electromigration failure of the interconnect structure. In addition, the undesired oxide layer
120
may be non-conductive to insulate the conductive diffusion barrier material
110
from enhancing the conductivity of the interconnect structure. Such features are especially disadvantageous for interconnect structures having higher aspect ratio (defined as a ratio of the depth to the width of the interconnect structure).
Thus, as integrated circuit dimensions including the width of the interconnect structures are further scaled down, a mechanism is desired for eliminating the undesired oxide layer
120
from the interconnect structure. In addition, preservation of any dielectric material of the integrated circuit having the interconnect structure is desired while eliminating the undesired oxide layer
120
from the interconnect structure.
SUMMARY OF THE INVENTION
Accordingly, in a general aspect of the present invention, a sacrificial layer of protective material is formed on an underlying material, such as the diffusion barrier material, to prevent oxidation of the underlying material.
In one embodiment of the present invention, in a system and method for filling an interconnect opening of an integrated circuit formed on a semiconductor substrate, an underlying material is formed at any exposed walls of the interconnect opening. A sacrificial layer of protective material is formed on the underlying material at the walls of the interconnect opening. The underlying material and the sacrificial layer of protective material are formed without a vacuum break. The protective material of the sacrificial layer is soluble in an acidic catalytic solution used for depositing a catalytic seed layer. The semiconductor substrate having the interconnect opening is placed within an acidic catalytic solution for depositing a catalytic

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